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https://sourceware.org/git/binutils-gdb.git
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b8a9943dd4
(extract.o): Pass -DSCACHE_P.
* mloop.in (extract{16,32}): Update call to m32r_decode.
* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
* sim-main.h: #include "ansidecl.h".
Don't include cpu-opc.h, done by arch.h.
start-sanitize-m32rx
* Makefile.in (M32RX_OBJS): Build m32rx support now.
(m32rx.o): New rule.
* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
(m32rx_h_accums_get): New function.
* mloopx.in: Update call to m32rx_decode. Rewrite exec loop.
* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
end-sanitize-m32rx
1363 lines
35 KiB
C
1363 lines
35 KiB
C
/* CPU family header for m32rx.
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This file is machine generated with CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef CPU_M32RX_H
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#define CPU_M32RX_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 2
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 2
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* general registers */
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SI h_gr[16];
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#define GET_H_GR(a1) CPU (h_gr)[a1]
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#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
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/* control registers */
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SI h_cr[7];
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#define GET_H_CR(a1) CPU (h_cr)[a1]
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#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
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/* accumulator */
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DI h_accum;
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#define GET_H_ACCUM() CPU (h_accum)
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#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
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/* start-sanitize-m32rx */
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/* accumulators */
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DI h_accums[2];
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/* end-sanitize-m32rx */
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#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
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#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
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/* start-sanitize-m32rx */
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/* abort flag */
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UBI h_abort;
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/* end-sanitize-m32rx */
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#define GET_H_ABORT() CPU (h_abort)
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#define SET_H_ABORT(x) (CPU (h_abort) = (x))
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/* condition bit */
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UBI h_cond;
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#define GET_H_COND() CPU (h_cond)
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#define SET_H_COND(x) (CPU (h_cond) = (x))
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/* sm */
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UBI h_sm;
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#define GET_H_SM() CPU (h_sm)
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#define SET_H_SM(x) (CPU (h_sm) = (x))
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/* bsm */
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UBI h_bsm;
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#define GET_H_BSM() CPU (h_bsm)
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#define SET_H_BSM(x) (CPU (h_bsm) = (x))
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/* ie */
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UBI h_ie;
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#define GET_H_IE() CPU (h_ie)
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#define SET_H_IE(x) (CPU (h_ie) = (x))
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/* bie */
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UBI h_bie;
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#define GET_H_BIE() CPU (h_bie)
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#define SET_H_BIE(x) (CPU (h_bie) = (x))
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/* bcond */
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UBI h_bcond;
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#define GET_H_BCOND() CPU (h_bcond)
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#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
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/* bpc */
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SI h_bpc;
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#define GET_H_BPC() CPU (h_bpc)
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#define SET_H_BPC(x) (CPU (h_bpc) = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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/* CPU profiling state information. */
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struct {
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/* general registers */
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unsigned long h_gr;
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} profile;
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#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
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} M32RX_CPU_DATA;
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extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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unsigned int length;
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PCADDR addr;
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const struct cgen_insn *opcode;
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#if ! defined (SCACHE_P)
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insn_t insn;
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#endif
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/* cpu specific data follows */
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union {
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struct { /* e.g. add $dr,$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_0_add;
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struct { /* e.g. add3 $dr,$sr,#$slo16 */
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UINT f_r1;
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UINT f_r2;
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HI f_simm16;
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} fmt_1_add3;
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struct { /* e.g. and3 $dr,$sr,#$uimm16 */
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UINT f_r1;
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UINT f_r2;
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USI f_uimm16;
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} fmt_2_and3;
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struct { /* e.g. or3 $dr,$sr,#$ulo16 */
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UINT f_r1;
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UINT f_r2;
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UHI f_uimm16;
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} fmt_3_or3;
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struct { /* e.g. addi $dr,#$simm8 */
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UINT f_r1;
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SI f_simm8;
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} fmt_4_addi;
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struct { /* e.g. addv3 $dr,$sr,#$simm16 */
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UINT f_r1;
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UINT f_r2;
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SI f_simm16;
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} fmt_5_addv3;
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struct { /* e.g. addx $dr,$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_6_addx;
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struct { /* e.g. bc $disp8 */
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IADDR f_disp8;
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} fmt_7_bc8;
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struct { /* e.g. bc $disp24 */
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IADDR f_disp24;
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} fmt_8_bc24;
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struct { /* e.g. beq $src1,$src2,$disp16 */
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UINT f_r1;
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UINT f_r2;
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IADDR f_disp16;
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} fmt_9_beq;
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struct { /* e.g. beqz $src2,$disp16 */
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UINT f_r2;
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IADDR f_disp16;
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} fmt_10_beqz;
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struct { /* e.g. bl $disp8 */
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IADDR f_disp8;
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} fmt_11_bl8;
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struct { /* e.g. bl $disp24 */
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IADDR f_disp24;
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} fmt_12_bl24;
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struct { /* e.g. bcl $disp8 */
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IADDR f_disp8;
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} fmt_13_bcl8;
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struct { /* e.g. bcl $disp24 */
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IADDR f_disp24;
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} fmt_14_bcl24;
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struct { /* e.g. bra $disp8 */
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IADDR f_disp8;
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} fmt_15_bra8;
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struct { /* e.g. bra $disp24 */
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IADDR f_disp24;
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} fmt_16_bra24;
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struct { /* e.g. cmp $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_17_cmp;
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struct { /* e.g. cmpi $src2,#$simm16 */
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UINT f_r2;
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SI f_simm16;
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} fmt_18_cmpi;
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struct { /* e.g. cmpui $src2,#$uimm16 */
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UINT f_r2;
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USI f_uimm16;
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} fmt_19_cmpui;
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struct { /* e.g. cmpz $src2 */
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UINT f_r2;
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} fmt_20_cmpz;
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struct { /* e.g. div $dr,$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_21_div;
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struct { /* e.g. jc $sr */
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UINT f_r2;
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} fmt_22_jc;
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struct { /* e.g. jl $sr */
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UINT f_r2;
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} fmt_23_jl;
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struct { /* e.g. jmp $sr */
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UINT f_r2;
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} fmt_24_jmp;
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struct { /* e.g. ld $dr,@$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_25_ld;
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struct { /* e.g. ld $dr,@($slo16,$sr) */
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UINT f_r1;
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UINT f_r2;
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HI f_simm16;
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} fmt_26_ld_d;
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struct { /* e.g. ldb $dr,@$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_27_ldb;
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struct { /* e.g. ldb $dr,@($slo16,$sr) */
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UINT f_r1;
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UINT f_r2;
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HI f_simm16;
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} fmt_28_ldb_d;
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struct { /* e.g. ldh $dr,@$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_29_ldh;
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struct { /* e.g. ldh $dr,@($slo16,$sr) */
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UINT f_r1;
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UINT f_r2;
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HI f_simm16;
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} fmt_30_ldh_d;
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struct { /* e.g. ld24 $dr,#$uimm24 */
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UINT f_r1;
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ADDR f_uimm24;
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} fmt_31_ld24;
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struct { /* e.g. ldi $dr,#$simm8 */
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UINT f_r1;
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SI f_simm8;
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} fmt_32_ldi8;
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struct { /* e.g. ldi $dr,$slo16 */
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UINT f_r1;
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HI f_simm16;
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} fmt_33_ldi16;
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struct { /* e.g. machi $src1,$src2,$acc */
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UINT f_r1;
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UINT f_acc;
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UINT f_r2;
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} fmt_34_machi_a;
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struct { /* e.g. mulhi $src1,$src2,$acc */
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UINT f_r1;
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UINT f_acc;
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UINT f_r2;
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} fmt_35_mulhi_a;
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struct { /* e.g. mv $dr,$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_36_mv;
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struct { /* e.g. mvfachi $dr,$accs */
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UINT f_r1;
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UINT f_accs;
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} fmt_37_mvfachi_a;
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struct { /* e.g. mvfc $dr,$scr */
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UINT f_r1;
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UINT f_r2;
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} fmt_38_mvfc;
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struct { /* e.g. mvtachi $src1,$accs */
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UINT f_r1;
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UINT f_accs;
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} fmt_39_mvtachi_a;
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struct { /* e.g. mvtc $sr,$dcr */
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UINT f_r1;
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UINT f_r2;
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} fmt_40_mvtc;
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struct { /* e.g. nop */
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int empty;
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} fmt_41_nop;
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struct { /* e.g. rac $accs */
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UINT f_accs;
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} fmt_42_rac_a;
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struct { /* e.g. rte */
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int empty;
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} fmt_43_rte;
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struct { /* e.g. seth $dr,#$hi16 */
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UINT f_r1;
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UHI f_hi16;
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} fmt_44_seth;
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struct { /* e.g. slli $dr,#$uimm5 */
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UINT f_r1;
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USI f_uimm5;
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} fmt_45_slli;
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struct { /* e.g. st $src1,@($slo16,$src2) */
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UINT f_r1;
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UINT f_r2;
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HI f_simm16;
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} fmt_46_st_d;
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struct { /* e.g. trap #$uimm4 */
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USI f_uimm4;
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} fmt_47_trap;
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struct { /* e.g. satb $dr,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_48_satb;
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struct { /* e.g. sat $dr,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_49_sat;
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struct { /* e.g. sadd */
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int empty;
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} fmt_50_sadd;
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struct { /* e.g. macwu1 $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_51_macwu1;
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struct { /* e.g. msblo $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_52_msblo;
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struct { /* e.g. sc */
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int empty;
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} fmt_53_sc;
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} fields;
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#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
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unsigned long h_gr_get;
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unsigned long h_gr_set;
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#endif
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};
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/* A cached insn.
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This is also used in the non-scache case. In this situation we assume
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the cache size is 1, and do a few things a little differently. */
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struct scache {
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IADDR next;
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union {
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#if ! WITH_SEM_SWITCH_FULL
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SEMANTIC_FN *sem_fn;
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#endif
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#if ! WITH_SEM_SWITCH_FAST
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#if WITH_SCACHE
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SEMANTIC_CACHE_FN *sem_fast_fn;
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#else
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SEMANTIC_FN *sem_fast_fn;
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#endif
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#endif
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#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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void *sem_case;
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#else
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int sem_case;
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#endif
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#endif
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} semantic;
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_FMT_0_ADD_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_FMT_0_ADD_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_1_ADD3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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int f_simm16; \
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unsigned int length;
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#define EXTRACT_FMT_1_ADD3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
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#define EXTRACT_FMT_2_AND3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_FMT_2_AND3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
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#define EXTRACT_FMT_3_OR3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_FMT_3_OR3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
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#define EXTRACT_FMT_4_ADDI_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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int f_simm8; \
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unsigned int length;
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#define EXTRACT_FMT_4_ADDI_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
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#define EXTRACT_FMT_5_ADDV3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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int f_simm16; \
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unsigned int length;
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#define EXTRACT_FMT_5_ADDV3_CODE \
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|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_6_ADDX_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_6_ADDX_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_7_BC8_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp8; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_7_BC8_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
|
|
|
#define EXTRACT_FMT_8_BC24_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp24; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_8_BC24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
|
|
|
#define EXTRACT_FMT_9_BEQ_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_disp16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_9_BEQ_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
|
|
|
|
#define EXTRACT_FMT_10_BEQZ_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_disp16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_10_BEQZ_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
|
|
|
|
#define EXTRACT_FMT_11_BL8_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp8; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_11_BL8_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
|
|
|
#define EXTRACT_FMT_12_BL24_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp24; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_12_BL24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
|
|
|
#define EXTRACT_FMT_13_BCL8_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp8; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_13_BCL8_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
|
|
|
#define EXTRACT_FMT_14_BCL24_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp24; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_14_BCL24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
|
|
|
#define EXTRACT_FMT_15_BRA8_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp8; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_15_BRA8_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
|
|
|
#define EXTRACT_FMT_16_BRA24_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_disp24; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_16_BRA24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
|
|
|
#define EXTRACT_FMT_17_CMP_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_17_CMP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_18_CMPI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_18_CMPI_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_19_CMPUI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_uimm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_19_CMPUI_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_20_CMPZ_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_20_CMPZ_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_21_DIV_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_21_DIV_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_22_JC_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_22_JC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_23_JL_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_23_JL_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_24_JMP_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_24_JMP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_25_LD_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_25_LD_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_26_LD_D_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_26_LD_D_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_27_LDB_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_27_LDB_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_28_LDB_D_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_28_LDB_D_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_29_LDH_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_29_LDH_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_30_LDH_D_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_30_LDH_D_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_31_LD24_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_uimm24; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_31_LD24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
|
|
|
|
#define EXTRACT_FMT_32_LDI8_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
int f_simm8; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_32_LDI8_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
|
|
|
|
#define EXTRACT_FMT_33_LDI16_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_33_LDI16_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_34_MACHI_A_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_acc; \
|
|
UINT f_op23; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_34_MACHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
|
|
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_35_MULHI_A_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_acc; \
|
|
UINT f_op23; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_35_MULHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
|
|
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_36_MV_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_36_MV_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_37_MVFACHI_A_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_accs; \
|
|
UINT f_op3; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_37_MVFACHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
|
|
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
|
|
|
|
#define EXTRACT_FMT_38_MVFC_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_38_MVFC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_39_MVTACHI_A_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_accs; \
|
|
UINT f_op3; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_39_MVTACHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
|
|
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
|
|
|
|
#define EXTRACT_FMT_40_MVTC_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_40_MVTC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_41_NOP_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_41_NOP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_42_RAC_A_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_accs; \
|
|
UINT f_op3; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_42_RAC_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
|
|
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
|
|
|
|
#define EXTRACT_FMT_43_RTE_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_43_RTE_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_44_SETH_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_hi16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_44_SETH_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_45_SLLI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_shift_op2; \
|
|
UINT f_uimm5; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_45_SLLI_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
|
|
f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
|
|
|
|
#define EXTRACT_FMT_46_ST_D_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
int f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_46_ST_D_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_47_TRAP_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_uimm4; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_47_TRAP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_48_SATB_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_uimm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_48_SATB_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_49_SAT_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_uimm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_49_SAT_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
|
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_FMT_50_SADD_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_50_SADD_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_51_MACWU1_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_51_MACWU1_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_52_MSBLO_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_52_MSBLO_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_FMT_53_SC_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_FMT_53_SC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
|
|
|
/* Fetched input values of an instruction. */
|
|
|
|
struct parallel_exec {
|
|
union {
|
|
struct { /* e.g. add $dr,$sr */
|
|
SI dr;
|
|
SI sr;
|
|
} fmt_0_add;
|
|
struct { /* e.g. add3 $dr,$sr,#$slo16 */
|
|
HI slo16;
|
|
SI sr;
|
|
} fmt_1_add3;
|
|
struct { /* e.g. and3 $dr,$sr,#$uimm16 */
|
|
SI sr;
|
|
USI uimm16;
|
|
} fmt_2_and3;
|
|
struct { /* e.g. or3 $dr,$sr,#$ulo16 */
|
|
SI sr;
|
|
UHI ulo16;
|
|
} fmt_3_or3;
|
|
struct { /* e.g. addi $dr,#$simm8 */
|
|
SI dr;
|
|
SI simm8;
|
|
} fmt_4_addi;
|
|
struct { /* e.g. addv3 $dr,$sr,#$simm16 */
|
|
SI simm16;
|
|
SI sr;
|
|
} fmt_5_addv3;
|
|
struct { /* e.g. addx $dr,$sr */
|
|
UBI condbit;
|
|
SI dr;
|
|
SI sr;
|
|
} fmt_6_addx;
|
|
struct { /* e.g. bc $disp8 */
|
|
UBI condbit;
|
|
IADDR disp8;
|
|
} fmt_7_bc8;
|
|
struct { /* e.g. bc $disp24 */
|
|
UBI condbit;
|
|
IADDR disp24;
|
|
} fmt_8_bc24;
|
|
struct { /* e.g. beq $src1,$src2,$disp16 */
|
|
IADDR disp16;
|
|
SI src1;
|
|
SI src2;
|
|
} fmt_9_beq;
|
|
struct { /* e.g. beqz $src2,$disp16 */
|
|
IADDR disp16;
|
|
SI src2;
|
|
} fmt_10_beqz;
|
|
struct { /* e.g. bl $disp8 */
|
|
IADDR disp8;
|
|
USI pc;
|
|
} fmt_11_bl8;
|
|
struct { /* e.g. bl $disp24 */
|
|
IADDR disp24;
|
|
USI pc;
|
|
} fmt_12_bl24;
|
|
struct { /* e.g. bcl $disp8 */
|
|
UBI condbit;
|
|
IADDR disp8;
|
|
USI pc;
|
|
} fmt_13_bcl8;
|
|
struct { /* e.g. bcl $disp24 */
|
|
UBI condbit;
|
|
IADDR disp24;
|
|
USI pc;
|
|
} fmt_14_bcl24;
|
|
struct { /* e.g. bra $disp8 */
|
|
IADDR disp8;
|
|
} fmt_15_bra8;
|
|
struct { /* e.g. bra $disp24 */
|
|
IADDR disp24;
|
|
} fmt_16_bra24;
|
|
struct { /* e.g. cmp $src1,$src2 */
|
|
SI src1;
|
|
SI src2;
|
|
} fmt_17_cmp;
|
|
struct { /* e.g. cmpi $src2,#$simm16 */
|
|
SI simm16;
|
|
SI src2;
|
|
} fmt_18_cmpi;
|
|
struct { /* e.g. cmpui $src2,#$uimm16 */
|
|
SI src2;
|
|
USI uimm16;
|
|
} fmt_19_cmpui;
|
|
struct { /* e.g. cmpz $src2 */
|
|
SI src2;
|
|
} fmt_20_cmpz;
|
|
struct { /* e.g. div $dr,$sr */
|
|
SI dr;
|
|
SI sr;
|
|
} fmt_21_div;
|
|
struct { /* e.g. jc $sr */
|
|
UBI condbit;
|
|
SI sr;
|
|
} fmt_22_jc;
|
|
struct { /* e.g. jl $sr */
|
|
USI pc;
|
|
SI sr;
|
|
} fmt_23_jl;
|
|
struct { /* e.g. jmp $sr */
|
|
SI sr;
|
|
} fmt_24_jmp;
|
|
struct { /* e.g. ld $dr,@$sr */
|
|
UQI h_memory_sr;
|
|
SI sr;
|
|
} fmt_25_ld;
|
|
struct { /* e.g. ld $dr,@($slo16,$sr) */
|
|
UQI h_memory_add_WI_sr_slo16;
|
|
HI slo16;
|
|
SI sr;
|
|
} fmt_26_ld_d;
|
|
struct { /* e.g. ldb $dr,@$sr */
|
|
UQI h_memory_sr;
|
|
SI sr;
|
|
} fmt_27_ldb;
|
|
struct { /* e.g. ldb $dr,@($slo16,$sr) */
|
|
UQI h_memory_add_WI_sr_slo16;
|
|
HI slo16;
|
|
SI sr;
|
|
} fmt_28_ldb_d;
|
|
struct { /* e.g. ldh $dr,@$sr */
|
|
UQI h_memory_sr;
|
|
SI sr;
|
|
} fmt_29_ldh;
|
|
struct { /* e.g. ldh $dr,@($slo16,$sr) */
|
|
UQI h_memory_add_WI_sr_slo16;
|
|
HI slo16;
|
|
SI sr;
|
|
} fmt_30_ldh_d;
|
|
struct { /* e.g. ld24 $dr,#$uimm24 */
|
|
ADDR uimm24;
|
|
} fmt_31_ld24;
|
|
struct { /* e.g. ldi $dr,#$simm8 */
|
|
SI simm8;
|
|
} fmt_32_ldi8;
|
|
struct { /* e.g. ldi $dr,$slo16 */
|
|
HI slo16;
|
|
} fmt_33_ldi16;
|
|
struct { /* e.g. machi $src1,$src2,$acc */
|
|
DI acc;
|
|
SI src1;
|
|
SI src2;
|
|
} fmt_34_machi_a;
|
|
struct { /* e.g. mulhi $src1,$src2,$acc */
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SI src1;
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SI src2;
|
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} fmt_35_mulhi_a;
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struct { /* e.g. mv $dr,$sr */
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|
SI sr;
|
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} fmt_36_mv;
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struct { /* e.g. mvfachi $dr,$accs */
|
|
DI accs;
|
|
} fmt_37_mvfachi_a;
|
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struct { /* e.g. mvfc $dr,$scr */
|
|
SI scr;
|
|
} fmt_38_mvfc;
|
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struct { /* e.g. mvtachi $src1,$accs */
|
|
DI accs;
|
|
SI src1;
|
|
} fmt_39_mvtachi_a;
|
|
struct { /* e.g. mvtc $sr,$dcr */
|
|
SI sr;
|
|
} fmt_40_mvtc;
|
|
struct { /* e.g. nop */
|
|
int empty;
|
|
} fmt_41_nop;
|
|
struct { /* e.g. rac $accs */
|
|
DI accs;
|
|
} fmt_42_rac_a;
|
|
struct { /* e.g. rte */
|
|
UBI h_bcond_0;
|
|
UBI h_bie_0;
|
|
SI h_bpc_0;
|
|
UBI h_bsm_0;
|
|
} fmt_43_rte;
|
|
struct { /* e.g. seth $dr,#$hi16 */
|
|
UHI hi16;
|
|
} fmt_44_seth;
|
|
struct { /* e.g. slli $dr,#$uimm5 */
|
|
SI dr;
|
|
USI uimm5;
|
|
} fmt_45_slli;
|
|
struct { /* e.g. st $src1,@($slo16,$src2) */
|
|
HI slo16;
|
|
SI src1;
|
|
SI src2;
|
|
} fmt_46_st_d;
|
|
struct { /* e.g. trap #$uimm4 */
|
|
USI uimm4;
|
|
} fmt_47_trap;
|
|
struct { /* e.g. satb $dr,$src2 */
|
|
SI src2;
|
|
} fmt_48_satb;
|
|
struct { /* e.g. sat $dr,$src2 */
|
|
UBI condbit;
|
|
SI src2;
|
|
} fmt_49_sat;
|
|
struct { /* e.g. sadd */
|
|
DI h_accums_0;
|
|
DI h_accums_1;
|
|
} fmt_50_sadd;
|
|
struct { /* e.g. macwu1 $src1,$src2 */
|
|
DI h_accums_1;
|
|
SI src1;
|
|
SI src2;
|
|
} fmt_51_macwu1;
|
|
struct { /* e.g. msblo $src1,$src2 */
|
|
DI accum;
|
|
SI src1;
|
|
SI src2;
|
|
} fmt_52_msblo;
|
|
struct { /* e.g. sc */
|
|
UBI condbit;
|
|
} fmt_53_sc;
|
|
} operands;
|
|
};
|
|
|
|
#endif /* CPU_M32RX_H */
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