mirror of
https://sourceware.org/git/binutils-gdb.git
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43234a1e14
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
323 lines
12 KiB
Plaintext
323 lines
12 KiB
Plaintext
// i386 register table.
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// Copyright 2007, 2008
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// Free Software Foundation, Inc.
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//
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// This file is part of the GNU opcodes library.
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//
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// This library is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3, or (at your option)
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// any later version.
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//
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// It is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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// License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GAS; see the file COPYING. If not, write to the Free
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// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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// Make %st first as we test for it.
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st, FloatReg|FloatAcc, 0, 0, 11, 33
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// 8 bit regs
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al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
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cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
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bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
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ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
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ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
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dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
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bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
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axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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// 16 bit regs
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ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
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cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
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dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
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bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
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// 32 bit regs
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eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
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ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Reg32, 0, 4, 4, Dw2Inval
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ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
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rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Reg64, 0, 4, Dw2Inval, 7
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rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
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// Vector mask registers.
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k0, RegMask, 0, 0, 93, 118
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k1, RegMask, 0, 1, 94, 119
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k2, RegMask, 0, 2, 95, 120
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k3, RegMask, 0, 3, 96, 121
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k4, RegMask, 0, 4, 97, 122
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k5, RegMask, 0, 5, 98, 123
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k6, RegMask, 0, 6, 99, 124
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k7, RegMask, 0, 7, 100, 125
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// Segment registers.
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es, SReg2, 0, 0, 40, 50
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cs, SReg2, 0, 1, 41, 51
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ss, SReg2, 0, 2, 42, 52
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ds, SReg2, 0, 3, 43, 53
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fs, SReg3, 0, 4, 44, 54
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gs, SReg3, 0, 5, 45, 55
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flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
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// Control registers.
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cr0, Control, 0, 0, Dw2Inval, Dw2Inval
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cr1, Control, 0, 1, Dw2Inval, Dw2Inval
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cr2, Control, 0, 2, Dw2Inval, Dw2Inval
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cr3, Control, 0, 3, Dw2Inval, Dw2Inval
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cr4, Control, 0, 4, Dw2Inval, Dw2Inval
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cr5, Control, 0, 5, Dw2Inval, Dw2Inval
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cr6, Control, 0, 6, Dw2Inval, Dw2Inval
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cr7, Control, 0, 7, Dw2Inval, Dw2Inval
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cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
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cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
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cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
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cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
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cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
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cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
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cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
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cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
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// Debug registers.
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db0, Debug, 0, 0, Dw2Inval, Dw2Inval
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db1, Debug, 0, 1, Dw2Inval, Dw2Inval
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db2, Debug, 0, 2, Dw2Inval, Dw2Inval
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db3, Debug, 0, 3, Dw2Inval, Dw2Inval
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db4, Debug, 0, 4, Dw2Inval, Dw2Inval
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db5, Debug, 0, 5, Dw2Inval, Dw2Inval
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db6, Debug, 0, 6, Dw2Inval, Dw2Inval
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db7, Debug, 0, 7, Dw2Inval, Dw2Inval
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db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
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dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
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dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
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dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
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dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
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dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
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dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
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dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
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dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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// Test registers.
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tr0, Test, 0, 0, Dw2Inval, Dw2Inval
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tr1, Test, 0, 1, Dw2Inval, Dw2Inval
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tr2, Test, 0, 2, Dw2Inval, Dw2Inval
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tr3, Test, 0, 3, Dw2Inval, Dw2Inval
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tr4, Test, 0, 4, Dw2Inval, Dw2Inval
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tr5, Test, 0, 5, Dw2Inval, Dw2Inval
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tr6, Test, 0, 6, Dw2Inval, Dw2Inval
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tr7, Test, 0, 7, Dw2Inval, Dw2Inval
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// MMX and simd registers.
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mm0, RegMMX, 0, 0, 29, 41
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mm1, RegMMX, 0, 1, 30, 42
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mm2, RegMMX, 0, 2, 31, 43
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mm3, RegMMX, 0, 3, 32, 44
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mm4, RegMMX, 0, 4, 33, 45
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mm5, RegMMX, 0, 5, 34, 46
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mm6, RegMMX, 0, 6, 35, 47
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mm7, RegMMX, 0, 7, 36, 48
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xmm0, RegXMM, 0, 0, 21, 17
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xmm1, RegXMM, 0, 1, 22, 18
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xmm2, RegXMM, 0, 2, 23, 19
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xmm3, RegXMM, 0, 3, 24, 20
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xmm4, RegXMM, 0, 4, 25, 21
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xmm5, RegXMM, 0, 5, 26, 22
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xmm6, RegXMM, 0, 6, 27, 23
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xmm7, RegXMM, 0, 7, 28, 24
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xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
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xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
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xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
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xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
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xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
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xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
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xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
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xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
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xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
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xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
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xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
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xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
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xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
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xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
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xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
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xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
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xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
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xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
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xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
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xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
|
|
xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
|
|
xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
|
|
xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
|
|
xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
|
|
// AVX registers.
|
|
ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
|
|
ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
|
|
ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
|
|
ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
|
|
ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
|
|
ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
|
|
ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
|
|
ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
|
|
ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
|
|
ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
|
|
ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
|
|
ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
|
|
ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
|
|
ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
|
|
ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
|
|
ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
|
|
ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval
|
|
ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval
|
|
ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval
|
|
ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval
|
|
ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval
|
|
ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval
|
|
ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval
|
|
ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval
|
|
ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
|
ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
|
ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
|
ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
|
ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
|
ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
|
ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
|
ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
|
// AVX512 registers.
|
|
zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval
|
|
zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval
|
|
zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval
|
|
zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval
|
|
zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval
|
|
zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval
|
|
zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval
|
|
zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval
|
|
zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval
|
|
zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval
|
|
zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval
|
|
zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval
|
|
zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval
|
|
zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval
|
|
zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval
|
|
zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval
|
|
zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval
|
|
zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval
|
|
zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval
|
|
zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval
|
|
zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval
|
|
zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval
|
|
zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval
|
|
zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval
|
|
zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
|
zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
|
zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
|
zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
|
zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
|
zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
|
zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
|
zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
|
// Bound registers for MPX
|
|
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
|
|
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
|
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
|
|
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
|
|
// No type will make these registers rejected for all purposes except
|
|
// for addressing. This saves creating one extra type for RIP/EIP.
|
|
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
|
|
eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
|
|
// No type will make these registers rejected for all purposes except
|
|
// for addressing.
|
|
riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
|
|
eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
|
|
// fp regs.
|
|
st(0), FloatReg|FloatAcc, 0, 0, 11, 33
|
|
st(1), FloatReg, 0, 1, 12, 34
|
|
st(2), FloatReg, 0, 2, 13, 35
|
|
st(3), FloatReg, 0, 3, 14, 36
|
|
st(4), FloatReg, 0, 4, 15, 37
|
|
st(5), FloatReg, 0, 5, 16, 38
|
|
st(6), FloatReg, 0, 6, 17, 39
|
|
st(7), FloatReg, 0, 7, 18, 40
|
|
// Pseudo-register names only used in .cfi_* directives
|
|
eflags, 0, 0, 0, 9, 49
|
|
rflags, 0, 0, 0, Dw2Inval, 49
|
|
fs.base, 0, 0, 0, Dw2Inval, 58
|
|
gs.base, 0, 0, 0, Dw2Inval, 59
|
|
tr, 0, 0, 0, 48, 62
|
|
ldtr, 0, 0, 0, 49, 63
|
|
// st0...7 for backward compatibility
|
|
st0, 0, 0, 0, 11, 33
|
|
st1, 0, 0, 1, 12, 34
|
|
st2, 0, 0, 2, 13, 35
|
|
st3, 0, 0, 3, 14, 36
|
|
st4, 0, 0, 4, 15, 37
|
|
st5, 0, 0, 5, 16, 38
|
|
st6, 0, 0, 6, 17, 39
|
|
st7, 0, 0, 7, 18, 40
|
|
fcw, 0, 0, 0, 37, 65
|
|
fsw, 0, 0, 0, 38, 66
|
|
mxcsr, 0, 0, 0, 39, 64
|