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fe944acf8f
bfd * Makefile.am: Added NFP files to build. * archures.c: Added bfd_arch_nfp * config.bfd: Added NFP support. * configure.ac: Added NFP support. * cpu-nfp.c: New, for NFP support. * elf-bfd.h: Added elf_section_info() * elf64-nfp.c: New, for NFP support. * po/SRC-POTFILES.in: Added NFP source files. * targets.c: Added nfp_elf64_vec * bfd-in2.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. binutils* readelf.c: Very basic support for EM_NFP and its section types. * testsuite/binutils-all/nfp: New directory. * testsuite/binutils-all/nfp/objdump.exp: New file. Run new tests. * testsuite/binutils-all/nfp/test2_ctx8.d: New file. * testsuite/binutils-all/nfp/test2_no-pc_ctx4.d: New file. * testsuite/binutils-all/nfp/test1.d: New file. * testsuite/binutils-all/nfp/nfp6000.nffw: New file. * testsuite/binutils-all/nfp/test2_nfp6000.nffw: New file. * NEWS: Mention the new support. include * dis-asm.h: Added print_nfp_disassembler_options prototype. * elf/common.h: Added EM_NFP, officially assigned. See Google Group Generic System V Application Binary Interface. * elf/nfp.h: New, for NFP support. * opcode/nfp.h: New, for NFP support. opcodes Makefile.am: Added nfp-dis.c. configure.ac: Added bfd_nfp_arch. disassemble.h: Added print_insn_nfp prototype. disassemble.c: Added ARCH_nfp and call to print_insn_nfp nfp-dis.c: New, for NFP support. po/POTFILES.in: Added nfp-dis.c to the list. Makefile.in: Regenerate. configure: Regenerate.
293 lines
11 KiB
C
Executable File
293 lines
11 KiB
C
Executable File
/* NFP ELF support for BFD.
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Copyright (C) 2017-2018 Free Software Foundation, Inc.
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Contributed by Francois H. Theron <francois.theron@netronome.com>
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef _ELF_NFP_H
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#define _ELF_NFP_H
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#include "bfd.h"
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#include "elf/common.h"
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#include "elf/reloc-macros.h"
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#include "bfd_stdint.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define ET_NFP_PARTIAL_REL (ET_LOPROC + ET_REL)
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#define ET_NFP_PARTIAL_EXEC (ET_LOPROC + ET_EXEC)
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/* NFP e_flags - chip family
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Valid values for FAMILY are:
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0x3200 - NFP-32xx
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0x6000 - NFP-6xxx/NFP-4xxx. */
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#define EF_NFP_MACH(ef_nfp) (((ef_nfp) >> 8) & 0xFFFF)
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#define EF_NFP_SET_MACH(nfp_fam) (((nfp_fam) & 0xFFFF) << 8)
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#define E_NFP_MACH_3200 0x3200
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#define E_NFP_MACH_6000 0x6000
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#define NFP_3200_CPPTGT_MSF0 1
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#define NFP_3200_CPPTGT_QDR 2
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#define NFP_3200_CPPTGT_MSF1 3
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#define NFP_3200_CPPTGT_HASH 4
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#define NFP_3200_CPPTGT_MU 7
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#define NFP_3200_CPPTGT_GS 8
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#define NFP_3200_CPPTGT_PCIE 9
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#define NFP_3200_CPPTGT_ARM 10
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#define NFP_3200_CPPTGT_CRYPTO 12
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#define NFP_3200_CPPTGT_CAP 13
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#define NFP_3200_CPPTGT_CT 14
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#define NFP_3200_CPPTGT_CLS 15
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#define NFP_6000_CPPTGT_NBI 1
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#define NFP_6000_CPPTGT_VQDR 2
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#define NFP_6000_CPPTGT_ILA 6
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#define NFP_6000_CPPTGT_MU 7
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#define NFP_6000_CPPTGT_PCIE 9
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#define NFP_6000_CPPTGT_ARM 10
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#define NFP_6000_CPPTGT_CRYPTO 12
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#define NFP_6000_CPPTGT_CTXPB 14
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#define NFP_6000_CPPTGT_CLS 15
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/* NFP Section types
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MECONFIG - NFP-32xx only, ME CSR configurations
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INITREG - A generic register initialisation section (chip or ME CSRs/GPRs)
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UDEBUG - Legacy-style debug data section. */
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#define SHT_NFP_MECONFIG (SHT_LOPROC + 1)
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#define SHT_NFP_INITREG (SHT_LOPROC + 2)
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#define SHT_NFP_UDEBUG SHT_LOUSER
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/* NFP SECTION flags
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ELF-64 sh_flags is 64-bit, but there is no info on what the upper 32 bits
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are expected to be used for, it is not marked reserved either.
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We'll use them for NFP-specific flags since we don't use ELF-32.
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INIT - Sections that are loaded and executed before the final text
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microcode. Non-code INIT sections are loaded first, then other
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memory secions, then INIT2 sections, then INIT-code sections.
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INIT2 - Sections that are loaded before INIT-code sections, used for
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transient configuration before executing INIT-code section
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microcode.
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SCS - The number of additional ME codestores being shared with the group's
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base ME of the section, e.g. 0 for no SCS, 1 for dual and 3 for
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quad. If this is 0 it is possible that stagger-style SCS codestore
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sections are being used. For stagger-style each section is simply
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loaded directly to the ME it is assigned to. If these flags are
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used, virtual address space loading will be used - one large section
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loaded to the group's base ME will be packed across shared MEs by
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hardware. This is not available on all ME versions.
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NFP_ELF_SHF_GET_SCS (val) returns the number of additional codestores
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being shared with the group's base ME, e.g. 0 for no SCS,
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1 for dual SCS, 3 for quad SCS. */
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#define SHF_NFP_INIT 0x80000000
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#define SHF_NFP_INIT2 0x40000000
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#define SHF_NFP_SCS(shf) (((shf) >> 32) & 0xFF)
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#define SHF_NFP_SET_SCS(v) (((BFD_HOST_U_64_BIT)((v) & 0xFF)) << 32)
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/* NFP Section Info
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For PROGBITS and NOBITS sections:
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MEMTYPE - the memory type
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DOMAIN - The island ID and ME number where the data will be loaded.
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For NFP-32xx, this is an island number or linear ME number.
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For NFP-6xxx, DOMAIN<15:8> == island ID, DOMAIN<7:0> is 0 based
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ME number (if applicable).
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For INITREG sections:
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ISLAND - island ID (if it's a ME target, ME numbers are in the
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section data)
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CPPTGT - CPP Target ID
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CPPACTRD - CPP Read Action
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CPPTOKRD - CPP Read Token
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CPPACTWR - CPP Write Action
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CPPTOKWR - CPP Write Token
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ORDER - Controls the order in which the loader processes sections with
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the same info fields. */
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#define SHI_NFP_DOMAIN(shi) (((shi) >> 16) & 0xFFFF)
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#define SHI_NFP_MEMTYPE(shi) ( (shi) & 0xFFFF)
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#define SHI_NFP_SET_DOMAIN(v) (((v) & 0xFFFF) << 16)
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#define SHI_NFP_SET_MEMTYPE(v) ( (v) & 0xFFFF)
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#define SHI_NFP_IREG_ISLAND(shi) (((shi) >> 26) & 0x3F)
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#define SHI_NFP_IREG_CPPTGT(shi) (((shi) >> 22) & 0xF)
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#define SHI_NFP_IREG_CPPACTRD(shi) (((shi) >> 17) & 0x1F)
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#define SHI_NFP_IREG_CPPTOKRD(shi) (((shi) >> 15) & 0x3)
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#define SHI_NFP_IREG_CPPACTWR(shi) (((shi) >> 10) & 0x1F)
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#define SHI_NFP_IREG_CPPTOKWR(shi) (((shi) >> 8) & 0x3)
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#define SHI_NFP_IREG_ORDER(shi) ( (shi) & 0xFF)
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#define SHI_NFP_SET_IREG_ISLAND(v) (((v) & 0x3F) << 26)
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#define SHI_NFP_SET_IREG_CPPTGT(v) (((v) & 0xF) << 22)
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#define SHI_NFP_SET_IREG_CPPACTRD(v) (((v) & 0x1F) << 17)
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#define SHI_NFP_SET_IREG_CPPTOKRD(v) (((v) & 0x3) << 15)
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#define SHI_NFP_SET_IREG_CPPACTWR(v) (((v) & 0x1F) << 10)
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#define SHI_NFP_SET_IREG_CPPTOKWR(v) (((v) & 0x3) << 8)
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#define SHI_NFP_SET_IREG_ORDER(v) ( (v) & 0xFF)
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/* CtXpb/reflect_read_sig_init/reflect_write_sig_init
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identifies Init-CSR sections for ME CSRs. */
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#define SHI_NFP_6000_IS_IREG_MECSR(shi) ( \
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SHI_NFP_IREG_CPPTGT (shi) == NFP_6000_CPPTGT_CTXPB \
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&& SHI_NFP_IREG_CPPACTRD (shi) == 2 \
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&& SHI_NFP_IREG_CPPTOKRD (shi) == 1 \
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&& SHI_NFP_IREG_CPPACTWR (shi) == 3 \
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&& SHI_NFP_IREG_CPPTOKWR (shi) == 1 \
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)
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/* Transient INITREG sections will be validated against the target
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but will not be kept - validate, write or read and discard.
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They will still be handled last (in order). */
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#define SHI_NFP_IREG_ORDER_TRANSIENT 0xFF
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/* Below are some extra macros to translate SHI fields in more specific
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contexts.
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For NFP-32xx, DOMAIN is set to a global linear ME number (0 to 39).
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An NFP-32xx has 8 MEs per island and up to 5 islands. */
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#define SHI_NFP_3200_ISLAND(shi) ((SHI_NFP_DOMAIN (shi) >> 3) & 0x7)
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#define SHI_NFP_3200_MENUM(shi) ( SHI_NFP_DOMAIN (shi) & 0x7)
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#define SHI_NFP_SET_3200_ISLAND(v) SHI_NFP_SET_DOMAIN (((v) & 0x7) << 3)
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#define SHI_NFP_SET_3200_MENUM(v) SHI_NFP_SET_DOMAIN ( (v) & 0x7)
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#define SHI_NFP_ISLAND(shi) ((SHI_NFP_DOMAIN (shi) >> 8) & 0xFF)
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#define SHI_NFP_MENUM(shi) ( SHI_NFP_DOMAIN (shi) & 0xFF)
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#define SHI_NFP_SET_ISLAND(shi) SHI_NFP_SET_DOMAIN (((shi) & 0xFF) << 8)
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#define SHI_NFP_SET_MENUM(shi) SHI_NFP_SET_DOMAIN ( (shi) & 0xFF)
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#define SHI_NFP_MEMTYPE_NONE 0
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#define SHI_NFP_MEMTYPE_USTORE 1
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#define SHI_NFP_MEMTYPE_LMEM 2
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#define SHI_NFP_MEMTYPE_CLS 3
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#define SHI_NFP_MEMTYPE_DRAM 4
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#define SHI_NFP_MEMTYPE_MU 4
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#define SHI_NFP_MEMTYPE_SRAM 5
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#define SHI_NFP_MEMTYPE_GS 6
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#define SHI_NFP_MEMTYPE_PPC_LMEM 7
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#define SHI_NFP_MEMTYPE_PPC_SMEM 8
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#define SHI_NFP_MEMTYPE_EMU_CACHE 9
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/* VTP_FORCE is for use by the NFP Linker+Loader only. */
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#define NFP_IREG_VTP_FORCE 0
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#define NFP_IREG_VTP_CONST 1
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#define NFP_IREG_VTP_REQUIRED 2
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#define NFP_IREG_VTP_VOLATILE_INIT 3
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#define NFP_IREG_VTP_VOLATILE_NOINIT 4
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#define NFP_IREG_VTP_INVALID 5
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/* Init-CSR entry w0 fields:
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NLW - Not Last Word
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CTX - ME context number (if applicable)
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VTP - Value type
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COH - CPP Offset High 8 bits. */
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#define NFP_IREG_ENTRY_WO_NLW(w0) (((w0) >> 31) & 0x1)
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#define NFP_IREG_ENTRY_WO_CTX(w0) (((w0) >> 28) & 0x7)
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#define NFP_IREG_ENTRY_WO_VTP(w0) (((w0) >> 25) & 0x7)
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#define NFP_IREG_ENTRY_WO_COH(w0) (((w0) >> 0) & 0xFF)
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typedef struct
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{
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uint32_t w0;
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uint32_t cpp_offset_lo;
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uint32_t val;
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uint32_t mask;
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} Elf_Nfp_InitRegEntry;
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typedef struct
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{
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uint32_t ctx_enables;
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uint32_t entry;
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uint32_t misc_control;
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uint32_t reserved;
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} Elf_Nfp_MeConfig;
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/* Relocations. */
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START_RELOC_NUMBERS (elf_nfp3200_reloc_type)
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RELOC_NUMBER (R_NFP3200_NOTYPE, 0)
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RELOC_NUMBER (R_NFP3200_W32LE, 1)
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RELOC_NUMBER (R_NFP3200_SRC8_A, 2)
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RELOC_NUMBER (R_NFP3200_SRC8_B, 3)
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RELOC_NUMBER (R_NFP3200_IMMED8_I, 4)
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RELOC_NUMBER (R_NFP3200_SC, 5)
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RELOC_NUMBER (R_NFP3200_IMMED_LO16_I_A, 6)
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RELOC_NUMBER (R_NFP3200_IMMED_LO16_I_B, 7)
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RELOC_NUMBER (R_NFP3200_SRC7_B, 8)
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RELOC_NUMBER (R_NFP3200_SRC7_A, 9)
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RELOC_NUMBER (R_NFP3200_SRC8_I_B, 10)
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RELOC_NUMBER (R_NFP3200_SRC8_I_A, 11)
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RELOC_NUMBER (R_NFP3200_IMMED_HI16_I_A, 12)
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RELOC_NUMBER (R_NFP3200_IMMED_HI16_I_B, 13)
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RELOC_NUMBER (R_NFP3200_RSVD_0, 14)
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RELOC_NUMBER (R_NFP3200_RSVD_1, 15)
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RELOC_NUMBER (R_NFP3200_RSVD_2, 16)
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RELOC_NUMBER (R_NFP3200_RSVD_3, 17)
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RELOC_NUMBER (R_NFP3200_RSVD_4, 18)
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RELOC_NUMBER (R_NFP3200_RSVD_5, 19)
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RELOC_NUMBER (R_NFP3200_RSVD_6, 20)
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RELOC_NUMBER (R_NFP3200_W64LE, 21)
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RELOC_NUMBER (R_NFP3200_W32BE, 22)
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RELOC_NUMBER (R_NFP3200_W64BE, 23)
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RELOC_NUMBER (R_NFP3200_W32LE_AND, 24)
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RELOC_NUMBER (R_NFP3200_W32BE_AND, 25)
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RELOC_NUMBER (R_NFP3200_W32LE_OR, 26)
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RELOC_NUMBER (R_NFP3200_W32BE_OR, 27)
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RELOC_NUMBER (R_NFP3200_W64LE_AND, 28)
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RELOC_NUMBER (R_NFP3200_W64BE_AND, 29)
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RELOC_NUMBER (R_NFP3200_W64LE_OR, 30)
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RELOC_NUMBER (R_NFP3200_W64BE_OR, 31)
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END_RELOC_NUMBERS (R_NFP3200_MAX)
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START_RELOC_NUMBERS (elf_nfp_reloc_type)
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RELOC_NUMBER (R_NFP_NOTYPE, 0)
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RELOC_NUMBER (R_NFP_W32LE, 1)
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RELOC_NUMBER (R_NFP_SRC8_A, 2)
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RELOC_NUMBER (R_NFP_SRC8_B, 3)
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RELOC_NUMBER (R_NFP_IMMED8_I, 4)
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RELOC_NUMBER (R_NFP_SC, 5)
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RELOC_NUMBER (R_NFP_IMMED_LO16_I_A, 6)
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RELOC_NUMBER (R_NFP_IMMED_LO16_I_B, 7)
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RELOC_NUMBER (R_NFP_SRC7_B, 8)
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RELOC_NUMBER (R_NFP_SRC7_A, 9)
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RELOC_NUMBER (R_NFP_SRC8_I_B, 10)
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RELOC_NUMBER (R_NFP_SRC8_I_A, 11)
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RELOC_NUMBER (R_NFP_IMMED_HI16_I_A, 12)
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RELOC_NUMBER (R_NFP_IMMED_HI16_I_B, 13)
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RELOC_NUMBER (R_NFP_W64LE, 14)
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RELOC_NUMBER (R_NFP_SH_INFO, 15)
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RELOC_NUMBER (R_NFP_W32BE, 16)
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RELOC_NUMBER (R_NFP_W64BE, 17)
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RELOC_NUMBER (R_NFP_W32_29_24, 18)
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RELOC_NUMBER (R_NFP_W32LE_AND, 19)
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RELOC_NUMBER (R_NFP_W32BE_AND, 20)
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RELOC_NUMBER (R_NFP_W32LE_OR, 21)
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RELOC_NUMBER (R_NFP_W32BE_OR, 22)
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RELOC_NUMBER (R_NFP_W64LE_AND, 23)
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RELOC_NUMBER (R_NFP_W64BE_AND, 24)
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RELOC_NUMBER (R_NFP_W64LE_OR, 25)
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RELOC_NUMBER (R_NFP_W64BE_OR, 26)
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END_RELOC_NUMBERS (R_NFP_MAX)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ELF_NFP_H */
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