mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-02-05 12:53:16 +08:00
248bf6de04
SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu <hau.hsu@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com> |
||
|---|---|---|
| .. | ||
| aarch64.h | ||
| alpha.h | ||
| arc-attrs.h | ||
| arc-func.h | ||
| arc.h | ||
| arm.h | ||
| avr.h | ||
| bfin.h | ||
| bpf.h | ||
| cgen.h | ||
| ChangeLog-0415 | ||
| ChangeLog-9103 | ||
| convex.h | ||
| cr16.h | ||
| cris.h | ||
| crx.h | ||
| csky.h | ||
| d10v.h | ||
| d30v.h | ||
| dlx.h | ||
| ft32.h | ||
| h8300.h | ||
| hppa.h | ||
| i386.h | ||
| ia64.h | ||
| kvx.h | ||
| loongarch.h | ||
| m68hc11.h | ||
| m68k.h | ||
| metag.h | ||
| mips.h | ||
| mmix.h | ||
| mn10200.h | ||
| mn10300.h | ||
| moxie.h | ||
| msp430-decode.h | ||
| msp430.h | ||
| nds32.h | ||
| nfp.h | ||
| nios2.h | ||
| nios2r1.h | ||
| nios2r2.h | ||
| np1.h | ||
| ns32k.h | ||
| pdp11.h | ||
| pj.h | ||
| pn.h | ||
| ppc.h | ||
| pru.h | ||
| pyr.h | ||
| riscv-opc.h | ||
| riscv.h | ||
| rl78.h | ||
| rx.h | ||
| s12z.h | ||
| s390.h | ||
| score-datadep.h | ||
| score-inst.h | ||
| sparc.h | ||
| spu-insns.h | ||
| spu.h | ||
| tic4x.h | ||
| tic6x-control-registers.h | ||
| tic6x-insn-formats.h | ||
| tic6x-opcode-table.h | ||
| tic6x.h | ||
| tic30.h | ||
| tic54x.h | ||
| tilegx.h | ||
| tilepro.h | ||
| v850.h | ||
| vax.h | ||
| visium.h | ||
| wasm.h | ||
| xgate.h | ||