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6327658ee7
This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
138 lines
5.7 KiB
C
138 lines
5.7 KiB
C
/* aarch64-dis.h -- Header file for aarch64-dis.c and aarch64-dis-2.c.
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Copyright (C) 2012-2021 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_DIS_H
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#define OPCODES_AARCH64_DIS_H
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#include <stdint.h>
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#include "aarch64-opc.h"
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/* Lookup opcode WORD in the opcode table.
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In the case of multiple aarch64_opcode candidates, one of them will be
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returned; for other candidate(s), call aarch64_find_next_opcode to
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obtain. Note that aarch64_find_next_opcode finds the next
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aarch64_opcode candidate in a way as if all related aarch64_opcode
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entries were in a single-link list.
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N.B. all alias opcodes are ignored here. */
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const aarch64_opcode* aarch64_opcode_lookup (uint32_t);
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const aarch64_opcode* aarch64_find_next_opcode (const aarch64_opcode *);
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/* Given OPCODE, return its alias, e.g. given UBFM, return LSL.
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In the case of multiple alias candidates, the one of the highest priority
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(or one of several aliases of the same highest priority) will be
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returned; for the other candidate(s), call aarch64_find_next_alias_opcode
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to obtain. Note that aarch64_find_next_alias_opcode finds the next
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alias candidate in a way as if all related aliases were in a single-link
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list with priority from the highest to the least. */
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const aarch64_opcode* aarch64_find_alias_opcode (const aarch64_opcode *);
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const aarch64_opcode* aarch64_find_next_alias_opcode (const aarch64_opcode *);
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/* Switch-table-based high-level operand extractor. */
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bool
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aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
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const aarch64_insn, const aarch64_inst *,
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aarch64_operand_error *);
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/* Operand extractors. */
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#define AARCH64_DECL_OPD_EXTRACTOR(x) \
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bool aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
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const aarch64_insn, const aarch64_inst *, \
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aarch64_operand_error *)
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AARCH64_DECL_OPD_EXTRACTOR (ext_none);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reglane);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist_r);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_elemlist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_shift);
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AARCH64_DECL_OPD_EXTRACTOR (ext_shll_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_half);
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AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_modified);
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AARCH64_DECL_OPD_EXTRACTOR (ext_fpimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_fbits);
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AARCH64_DECL_OPD_EXTRACTOR (ext_aimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm10);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_uimm12);
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AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
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AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
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AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
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AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
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AARCH64_DECL_OPD_EXTRACTOR (ext_barrier_dsb_nxs);
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AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
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AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_u6);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rr_lsl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rz_xtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zi_u5);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_lsl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
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AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30);
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#undef AARCH64_DECL_OPD_EXTRACTOR
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#endif /* OPCODES_AARCH64_DIS_H */
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