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e409955ddc
VDUP (neon) instructions can be conditional, but this is not taken into account in the current master. This commit fixes that by i) fixing the VDUP instruction masks and ii) adding logic for disassembling conditional neon instructions. opcodes * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. (print_insn_neon): Support disassembly of conditional instructions. binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that conditional VDUP instructions are disassembled correctly. * testsuite/binutils-all/arm/vdup-cond.s: New file used by vdup-cond.d. * testsuite/binutils-all/arm/vdup-thumb.d: New test for testing that VDUP instructions (which are conditional in A32) can be disassembled in thumb mode. * testsuite/binutils-all/arm/vdup-cond.s: New file used by vdup-thumb.d.
28 lines
756 B
Makefile
28 lines
756 B
Makefile
#PROG: objcopy
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#source vdup-cond.s
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#as: -mfpu=neon
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#objdump: -d
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#skip: *-*-pe *-wince-* *-*-coff
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#name: Check if disassembler can handle conditional neon (vdup) instructions
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.*: +file format .*arm.*
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Disassembly of section \.vdups:
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.+ <\.vdups>:
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[^:]+: 0e800b10 vdupeq.32 d0, r0
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[^:]+: 1e800b10 vdupne.32 d0, r0
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[^:]+: 2e800b10 vdupcs.32 d0, r0
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[^:]+: 3e800b10 vdupcc.32 d0, r0
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[^:]+: 4e800b10 vdupmi.32 d0, r0
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[^:]+: 5e800b10 vduppl.32 d0, r0
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[^:]+: 6e800b10 vdupvs.32 d0, r0
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[^:]+: 7e800b10 vdupvc.32 d0, r0
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[^:]+: 8e800b10 vduphi.32 d0, r0
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[^:]+: 9e800b10 vdupls.32 d0, r0
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[^:]+: ae800b10 vdupge.32 d0, r0
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[^:]+: be800b10 vduplt.32 d0, r0
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[^:]+: ce800b10 vdupgt.32 d0, r0
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[^:]+: de800b10 vduple.32 d0, r0
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[^:]+: ee800b10 vdup.32 d0, r0
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