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3b9fce9660
For the RISC-V target it is desirable if the three floating pointer status CSRs fflags, frm, and fcsr can be placed into either the FPU feature or the CSR feature. This allows different targets to build the features in a way that better reflects their target. The change to support this within GDB is fairly simple, so this is done in this commit, and some tests added to check this new functionality. gdb/ChangeLog: * riscv-tdep.c (value_of_riscv_user_reg): Moved to here from later in the file. (class riscv_pending_register_alias): Likewise. (riscv_register_feature::register_info): Change 'required_p' field to 'required', and change its type. Add 'check' member function. (riscv_register_feature::register_info::check): Define new member function. (riscv_xreg_feature): Change initialisation of 'required' field. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_check_tdesc_feature): Take extra parameter, the csr tdesc_feature, rewrite the function to use the new riscv_register_feature::register_info::check function. (riscv_gdbarch_init): Pass the csr tdesc_feature where needed. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-loading-01.xml: New file. * gdb.arch/riscv-tdesc-loading-02.xml: New file. * gdb.arch/riscv-tdesc-loading-03.xml: New file. * gdb.arch/riscv-tdesc-loading-04.xml: New file. * gdb.arch/riscv-tdesc-loading.exp: New file.
82 lines
3.7 KiB
XML
82 lines
3.7 KiB
XML
<?xml version="1.0"?>
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>riscv</architecture>
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<feature name="org.gnu.gdb.riscv.cpu">
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<reg name="zero" bitsize="64" type="int"/>
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<reg name="ra" bitsize="64" type="code_ptr"/>
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<reg name="sp" bitsize="64" type="data_ptr"/>
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<reg name="gp" bitsize="64" type="data_ptr"/>
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<reg name="tp" bitsize="64" type="data_ptr"/>
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<reg name="t0" bitsize="64" type="int"/>
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<reg name="t1" bitsize="64" type="int"/>
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<reg name="t2" bitsize="64" type="int"/>
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<reg name="fp" bitsize="64" type="data_ptr"/>
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<reg name="s1" bitsize="64" type="int"/>
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<reg name="a0" bitsize="64" type="int"/>
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<reg name="a1" bitsize="64" type="int"/>
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<reg name="a2" bitsize="64" type="int"/>
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<reg name="a3" bitsize="64" type="int"/>
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<reg name="a4" bitsize="64" type="int"/>
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<reg name="a5" bitsize="64" type="int"/>
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<reg name="a6" bitsize="64" type="int"/>
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<reg name="a7" bitsize="64" type="int"/>
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<reg name="s2" bitsize="64" type="int"/>
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<reg name="s3" bitsize="64" type="int"/>
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<reg name="s4" bitsize="64" type="int"/>
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<reg name="s5" bitsize="64" type="int"/>
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<reg name="s6" bitsize="64" type="int"/>
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<reg name="s7" bitsize="64" type="int"/>
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<reg name="s8" bitsize="64" type="int"/>
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<reg name="s9" bitsize="64" type="int"/>
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<reg name="s10" bitsize="64" type="int"/>
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<reg name="s11" bitsize="64" type="int"/>
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<reg name="t3" bitsize="64" type="int"/>
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<reg name="t4" bitsize="64" type="int"/>
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<reg name="t5" bitsize="64" type="int"/>
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<reg name="t6" bitsize="64" type="int"/>
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<reg name="pc" bitsize="64" type="code_ptr"/>
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</feature>
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<feature name="org.gnu.gdb.riscv.fpu">
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<union id="riscv_double">
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<field name="float" type="ieee_single"/>
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<field name="double" type="ieee_double"/>
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</union>
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<reg name="ft0" bitsize="64" type="riscv_double"/>
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<reg name="ft1" bitsize="64" type="riscv_double"/>
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<reg name="ft2" bitsize="64" type="riscv_double"/>
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<reg name="ft3" bitsize="64" type="riscv_double"/>
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<reg name="ft4" bitsize="64" type="riscv_double"/>
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<reg name="ft5" bitsize="64" type="riscv_double"/>
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<reg name="ft6" bitsize="64" type="riscv_double"/>
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<reg name="ft7" bitsize="64" type="riscv_double"/>
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<reg name="fs0" bitsize="64" type="riscv_double"/>
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<reg name="fs1" bitsize="64" type="riscv_double"/>
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<reg name="fa0" bitsize="64" type="riscv_double"/>
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<reg name="fa1" bitsize="64" type="riscv_double"/>
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<reg name="fa2" bitsize="64" type="riscv_double"/>
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<reg name="fa3" bitsize="64" type="riscv_double"/>
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<reg name="fa4" bitsize="64" type="riscv_double"/>
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<reg name="fa5" bitsize="64" type="riscv_double"/>
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<reg name="fa6" bitsize="64" type="riscv_double"/>
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<reg name="fa7" bitsize="64" type="riscv_double"/>
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<reg name="fs2" bitsize="64" type="riscv_double"/>
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<reg name="fs3" bitsize="64" type="riscv_double"/>
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<reg name="fs4" bitsize="64" type="riscv_double"/>
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<reg name="fs5" bitsize="64" type="riscv_double"/>
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<reg name="fs6" bitsize="64" type="riscv_double"/>
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<reg name="fs7" bitsize="64" type="riscv_double"/>
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<reg name="fs8" bitsize="64" type="riscv_double"/>
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<reg name="fs9" bitsize="64" type="riscv_double"/>
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<reg name="fs10" bitsize="64" type="riscv_double"/>
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<reg name="fs11" bitsize="64" type="riscv_double"/>
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<reg name="ft8" bitsize="64" type="riscv_double"/>
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<reg name="ft9" bitsize="64" type="riscv_double"/>
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<reg name="ft10" bitsize="64" type="riscv_double"/>
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<reg name="ft11" bitsize="64" type="riscv_double"/>
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<reg name="fflags" bitsize="32" type="int"/>
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<reg name="frm" bitsize="32" type="int"/>
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<reg name="fcsr" bitsize="32" type="int"/>
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</feature>
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</target>
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