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1003 lines
24 KiB
ArmAsm
1003 lines
24 KiB
ArmAsm
; This testcase is part of GDB, the GNU debugger.
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; Copyright 2017-2021 Free Software Foundation, Inc.
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see <http://www.gnu.org/licenses/>.
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.section .text
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.global main
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#define TEST_J
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#define TEST_JCC
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#define TEST_JL
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#define TEST_JLCC
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#define TEST_B
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#define TEST_BBIT
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#define TEST_BCC
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#define TEST_BI
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#define TEST_BL
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#define TEST_BRCC
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#define TEST_JLI
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#define TEST_LEAVE_S
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#define TEST_LPCC
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; JLI-specific stuff
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#ifdef TEST_JLI
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jli_table:
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.word 0xdeadbeea
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.word 0xdeadbeea
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jli_target:
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.word 0xdeadbeea
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.word 0xdeadbeea
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.set jli_offset, 3
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#endif
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main:
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; Each test case requires several symbols to be set, that identify expected
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; parameters of this instruction. Required symbols:
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; ${test}_start: symbol points to start of the test
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; ${test}_end: symbol points to the instruction after the jump/branch
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; instruction.
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; ${test}_target: branch target address.
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; ${test}_has_delay_slot: whether instruction has delay slot.
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; ${test}_cc: condition code numeric value.
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.set r12_value, 0xdead0000
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.set blink_value, 0xdead0004
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.set limm_value, 0xdead0008
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; Just an integer
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.set r4_value, 0xdead000c
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; Just an integer
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.set r5_value, 0xdead0010
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; offset index for BI [c]
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.set r7_value, 4
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.set u6_value, 0x20
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.set s12_target, 0x100
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mov r12, @r12_value
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mov r4, @r4_value
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mov r5, @r5_value
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mov r7, @r7_value
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mov blink, @blink_value
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#ifdef TEST_JLI
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; jli_base aux regnum = 0x290
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sr jli_table, [0x290]
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#endif
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start_branch_tests:
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#ifdef TEST_J
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#define TEST_NAME j_c
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; j [c]
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.set j_c_target, @r4_value
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.set j_c_has_delay_slot, 0
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.set j_c_cc, 0
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j_c_start:
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j [r4]
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j_c_end:
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; j [blink]
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.set j_blink_target, @blink_value
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.set j_blink_has_delay_slot, 0
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.set j_blink_cc, 0
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mov blink, @j_blink_target
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j_blink_start:
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j [blink]
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j_blink_end:
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; j limm
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.set j_limm_target, @limm_value
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.set j_limm_has_delay_slot, 0
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.set j_limm_cc, 0
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j_limm_start:
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j @j_limm_target
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j_limm_end:
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; j u6
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.set j_u6_target, @u6_value
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.set j_u6_has_delay_slot, 0
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.set j_u6_cc, 0
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j_u6_start:
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j @j_u6_target
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j_u6_end:
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; j s12
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.set j_s12_target, @s12_target
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.set j_s12_has_delay_slot, 0
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.set j_s12_cc, 0
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j_s12_start:
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j @j_s12_target
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j_s12_end:
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; j.d [c]
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.set j_d_c_target, @r4_value
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.set j_d_c_has_delay_slot, 1
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.set j_d_c_cc, 0
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j_d_c_start:
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j.d [r4]
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j_d_c_end:
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nop_s
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; j.d [blink]
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.set j_d_blink_target, @blink_value
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.set j_d_blink_has_delay_slot, 1
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.set j_d_blink_cc, 0
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j_d_blink_start:
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j.d [blink]
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j_d_blink_end:
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nop_s
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; j.d u6
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.set j_d_u6_target, @u6_value
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.set j_d_u6_has_delay_slot, 1
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.set j_d_u6_cc, 0
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j_d_u6_start:
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j.d @j_d_u6_target
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j_d_u6_end:
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nop_s
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; j.d s12
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.set j_d_s12_target, @s12_target
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.set j_d_s12_has_delay_slot, 1
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.set j_d_s12_cc, 0
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j_d_s12_start:
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j.d @j_d_s12_target
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j_d_s12_end:
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nop_s
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; j_s [b]
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.set j_s_b_target, @r12_value
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.set j_s_b_has_delay_slot, 0
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.set j_s_b_cc, 0
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j_s_b_start:
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j_s [r12]
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j_s_b_end:
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; j_s.d [b]
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.set j_s_d_b_target, @r12_value
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.set j_s_d_b_has_delay_slot, 1
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.set j_s_d_b_cc, 0
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j_s_d_b_start:
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j_s.d [r12]
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j_s_d_b_end:
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nop_s
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; j_s [blink]
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.set j_s_blink_target, @blink_value
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.set j_s_blink_has_delay_slot, 0
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.set j_s_blink_cc, 0
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j_s_blink_start:
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j_s [blink]
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j_s_blink_end:
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; j_s.d [blink]
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.set j_s_d_blink_target, @blink_value
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.set j_s_d_blink_has_delay_slot, 1
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.set j_c_cc, 0
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j_s_d_blink_start:
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j_s.d [blink]
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j_s_d_blink_end:
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nop_s
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#endif /* TEST_J */
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#ifdef TEST_JCC
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; jcc [c]
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.set jcc_c_target, @r4_value
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.set jcc_c_has_delay_slot, 0
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.set jcc_c_cc, 1
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jcc_c_start:
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jeq [r4]
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jcc_c_end:
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; jcc [blink]
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.set jcc_blink_target, @blink_value
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.set jcc_blink_has_delay_slot, 0
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.set jcc_blink_cc, 2
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jcc_blink_start:
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jnz [blink]
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jcc_blink_end:
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; jcc limm
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.set jcc_limm_target, @limm_value
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.set jcc_limm_has_delay_slot, 0
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.set jcc_limm_cc, 9
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jcc_limm_start:
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jgt @jcc_limm_target
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jcc_limm_end:
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; jcc u6
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.set jcc_u6_target, @u6_value
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.set jcc_u6_has_delay_slot, 0
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.set jcc_u6_cc, 0xA
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jcc_u6_start:
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jge @jcc_u6_target
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jcc_u6_end:
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; jcc.d [c]
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.set jcc_d_c_target, @r4_value
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.set jcc_d_c_has_delay_slot, 1
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.set jcc_d_c_cc, 0xB
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jcc_d_c_start:
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jlt.d [r4]
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jcc_d_c_end:
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nop_s
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; jcc.d [blink]
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.set jcc_d_blink_target, @blink_value
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.set jcc_d_blink_has_delay_slot, 1
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.set jcc_d_blink_cc, 0xC
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jcc_d_blink_start:
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jle.d [blink]
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jcc_d_blink_end:
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nop_s
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; jcc.d u6
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.set jcc_d_u6_target, @u6_value
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.set jcc_d_u6_has_delay_slot, 1
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.set jcc_d_u6_cc, 0xE
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jcc_d_u6_start:
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jls.d @jcc_d_u6_target
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jcc_d_u6_end:
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nop_s
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; jeq_s [blink]
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.set jcc_eq_s_blink_target, @blink_value
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.set jcc_eq_s_blink_has_delay_slot, 0
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.set jcc_eq_s_blink_cc, 1
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jcc_eq_s_blink_start:
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jeq_s [blink]
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jcc_eq_s_blink_end:
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; jne_s [blink]
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.set jcc_ne_s_blink_target, @blink_value
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.set jcc_ne_s_blink_has_delay_slot, 0
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.set jcc_ne_s_blink_cc, 2
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jcc_ne_s_blink_start:
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jne_s [blink]
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jcc_ne_s_blink_end:
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#endif /* TEST_JCC */
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#ifdef TEST_JL
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; jl [c]
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.set jl_c_target, @r4_value
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.set jl_c_has_delay_slot, 0
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.set jl_c_cc, 0
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jl_c_start:
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jl [r4]
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jl_c_end:
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; jl limm
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.set jl_limm_target, @limm_value
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.set jl_limm_has_delay_slot, 0
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.set jl_limm_cc, 0
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jl_limm_start:
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jl @jl_limm_target
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jl_limm_end:
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; jl u6
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.set jl_u6_target, @u6_value
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.set jl_u6_has_delay_slot, 0
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.set jl_u6_cc, 0
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jl_u6_start:
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jl @jl_u6_target
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jl_u6_end:
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; jl s12
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.set jl_s12_target, @s12_target
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.set jl_s12_has_delay_slot, 0
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.set jl_s12_cc, 0
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jl_s12_start:
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jl @jl_s12_target
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jl_s12_end:
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; jl.d [c]
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.set jl_d_c_target, @r4_value
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.set jl_d_c_has_delay_slot, 1
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.set jl_d_c_cc, 0
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jl_d_c_start:
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jl.d [r4]
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jl_d_c_end:
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nop_s
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; jl.d u6
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.set jl_d_u6_target, @u6_value
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.set jl_d_u6_has_delay_slot, 1
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.set jl_d_u6_cc, 0
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jl_d_u6_start:
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jl.d @jl_d_u6_target
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jl_d_u6_end:
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nop_s
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; jl.d s12
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.set jl_d_s12_target, @s12_target
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.set jl_d_s12_has_delay_slot, 1
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.set jl_d_s12_cc, 0
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jl_d_s12_start:
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jl.d @jl_d_s12_target
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jl_d_s12_end:
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nop_s
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; jl_s [b]
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.set jl_s_b_target, @r12_value
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.set jl_s_b_has_delay_slot, 0
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.set jl_s_b_cc, 0
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jl_s_b_start:
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jl_s [r12]
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jl_s_b_end:
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; jl_s.d [b]
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.set jl_s_d_b_target, @r12_value
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.set jl_s_d_b_has_delay_slot, 1
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.set jl_s_d_b_cc, 0
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jl_s_d_b_start:
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jl_s.d [r12]
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jl_s_d_b_end:
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nop_s
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#endif /* TEST_JL */
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#ifdef TEST_JLCC
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; jlcc [c]
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.set jlcc_c_target, @r4_value
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.set jlcc_c_has_delay_slot, 0
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.set jlcc_c_cc, 1
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jlcc_c_start:
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jleq [r4]
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jlcc_c_end:
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; jlcc limm
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.set jlcc_limm_target, @limm_value
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.set jlcc_limm_has_delay_slot, 0
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.set jlcc_limm_cc, 0x9
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jlcc_limm_start:
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jlgt @jlcc_limm_target
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jlcc_limm_end:
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; jlcc u6
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.set jlcc_u6_target, @u6_value
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.set jlcc_u6_has_delay_slot, 0
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.set jlcc_u6_cc, 0xA
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jlcc_u6_start:
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jlge @jlcc_u6_target
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jlcc_u6_end:
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; jlcc.d [c]
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.set jlcc_d_c_target, @r4_value
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.set jlcc_d_c_has_delay_slot, 1
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.set jlcc_d_c_cc, 0xB
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jlcc_d_c_start:
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jllt.d [r4]
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jlcc_d_c_end:
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nop_s
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; jlcc.d u6
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.set jlcc_d_u6_target, @u6_value
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.set jlcc_d_u6_has_delay_slot, 1
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.set jlcc_d_u6_cc, 0xE
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jlcc_d_u6_start:
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jlls.d @jlcc_d_u6_target
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jlcc_d_u6_end:
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nop_s
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#endif /* TEST_JLCC */
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#ifdef TEST_B
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.Lb_target:
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; Artifical nop, so that first b will not branch to itself.
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nop_s
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; b s25
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.set b_s25_target, @.Lb_target
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.set b_s25_has_delay_slot, 0
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.set b_s25_cc, 0
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b_s25_start:
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b @b_s25_target
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b_s25_end:
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; b.d s25
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.set b_d_s25_target, @.Lb_target
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.set b_d_s25_has_delay_slot, 1
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.set b_d_s25_cc, 0
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b_d_s25_start:
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b.d @b_d_s25_target
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b_d_s25_end:
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nop_s
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; b_s s10
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.set b_s_s10_target, @.Lb_target
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.set b_s_s10_has_delay_slot, 0
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.set b_s_s10_cc, 0
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b_s_s10_start:
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b_s @b_s_s10_target
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b_s_s10_end:
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#endif /* TEST_B */
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#ifdef TEST_BBIT
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; Due to specifics of bbit implementation in assembler, only local symbols can
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; be used as a branch targets for bbit and brcc.
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; bbits and brcc don't have condition code set to anything.
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.Lbbit_target:
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nop_s
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; bbit0.nt b,c,s9
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.set bbit0_nt_b_c_s9_target, @.Lbbit_target
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.set bbit0_nt_b_c_s9_has_delay_slot, 0
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.set bbit0_nt_b_c_s9_cc, 0
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bbit0_nt_b_c_s9_start:
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bbit0.nt r4,r5,@bbit0_nt_b_c_s9_target
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bbit0_nt_b_c_s9_end:
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; bbit0.d.nt b,c,s9
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.set bbit0_d_nt_b_c_s9_target, @.Lbbit_target
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.set bbit0_d_nt_b_c_s9_has_delay_slot, 1
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.set bbit0_d_nt_b_c_s9_cc, 0
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bbit0_d_nt_b_c_s9_start:
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bbit0.d.nt r4,r5,@.Lbbit_target
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bbit0_d_nt_b_c_s9_end:
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nop_s
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; bbit0.t b,c,s9
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.set bbit0_t_b_c_s9_target, @.Lbbit_target
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.set bbit0_t_b_c_s9_has_delay_slot, 0
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.set bbit0_t_b_c_s9_cc, 0
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bbit0_t_b_c_s9_start:
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bbit0.t r4,r5,@.Lbbit_target
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bbit0_t_b_c_s9_end:
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; bbit0.d.t b,c,s9
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.set bbit0_d_t_b_c_s9_target, @.Lbbit_target
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.set bbit0_d_t_b_c_s9_has_delay_slot, 1
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.set bbit0_d_t_b_c_s9_cc, 0
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bbit0_d_t_b_c_s9_start:
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bbit0.d.t r4,r5,@.Lbbit_target
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bbit0_d_t_b_c_s9_end:
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nop_s
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; bbit0.nt b,u6,s9
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.set bbit0_nt_b_u6_s9_target, @.Lbbit_target
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.set bbit0_nt_b_u6_s9_has_delay_slot, 0
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.set bbit0_nt_b_u6_s9_cc, 0
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bbit0_nt_b_u6_s9_start:
|
|
bbit0.nt r4,u6_value,@.Lbbit_target
|
|
bbit0_nt_b_u6_s9_end:
|
|
|
|
; bbit0.d.nt b,u6,s9
|
|
.set bbit0_d_nt_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit0_d_nt_b_u6_s9_has_delay_slot, 1
|
|
.set bbit0_d_nt_b_u6_s9_cc, 0
|
|
bbit0_d_nt_b_u6_s9_start:
|
|
bbit0.d.nt r4,u6_value,@.Lbbit_target
|
|
bbit0_d_nt_b_u6_s9_end:
|
|
nop_s
|
|
|
|
; bbit0.nt b,u6,s9
|
|
.set bbit0_t_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit0_t_b_u6_s9_has_delay_slot, 0
|
|
.set bbit0_t_b_u6_s9_cc, 0
|
|
bbit0_t_b_u6_s9_start:
|
|
bbit0.t r4,u6_value,@.Lbbit_target
|
|
bbit0_t_b_u6_s9_end:
|
|
|
|
; bbit0.d.nt b,u6,s9
|
|
.set bbit0_d_t_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit0_d_t_b_u6_s9_has_delay_slot, 1
|
|
.set bbit0_d_t_b_u6_s9_cc, 0
|
|
bbit0_d_t_b_u6_s9_start:
|
|
bbit0.d.t r4,u6_value,@.Lbbit_target
|
|
bbit0_d_t_b_u6_s9_end:
|
|
nop_s
|
|
|
|
; bbit0.nt b,limm,s9
|
|
.set bbit0_nt_b_limm_s9_target, @.Lbbit_target
|
|
.set bbit0_nt_b_limm_s9_has_delay_slot, 0
|
|
.set bbit0_nt_b_limm_s9_cc, 0
|
|
bbit0_nt_b_limm_s9_start:
|
|
bbit0.nt r4,limm_value,@.Lbbit_target
|
|
bbit0_nt_b_limm_s9_end:
|
|
|
|
; bbit0.t b,limm,s9
|
|
.set bbit0_t_b_limm_s9_target, @.Lbbit_target
|
|
.set bbit0_t_b_limm_s9_has_delay_slot, 0
|
|
.set bbit0_t_b_limm_s9_cc, 0
|
|
bbit0_t_b_limm_s9_start:
|
|
bbit0.t r4,limm_value,@.Lbbit_target
|
|
bbit0_t_b_limm_s9_end:
|
|
|
|
; bbit0.nt limm,c,s9
|
|
.set bbit0_nt_limm_c_s9_target, @.Lbbit_target
|
|
.set bbit0_nt_limm_c_s9_has_delay_slot, 0
|
|
.set bbit0_nt_limm_c_s9_cc, 0
|
|
bbit0_nt_limm_c_s9_start:
|
|
bbit0.nt limm_value,r4,@.Lbbit_target
|
|
bbit0_nt_limm_c_s9_end:
|
|
|
|
; bbit0.t limm,c,s9
|
|
.set bbit0_t_limm_c_s9_target, @.Lbbit_target
|
|
.set bbit0_t_limm_c_s9_has_delay_slot, 0
|
|
.set bbit0_t_limm_c_s9_cc, 0
|
|
bbit0_t_limm_c_s9_start:
|
|
bbit0.t limm_value,r4,@.Lbbit_target
|
|
bbit0_t_limm_c_s9_end:
|
|
|
|
; bbit0.nt limm,u6,s9
|
|
.set bbit0_nt_limm_u6_s9_target, @.Lbbit_target
|
|
.set bbit0_nt_limm_u6_s9_has_delay_slot, 0
|
|
.set bbit0_nt_limm_u6_s9_cc, 0
|
|
bbit0_nt_limm_u6_s9_start:
|
|
bbit0.nt limm_value,u6_value,@.Lbbit_target
|
|
bbit0_nt_limm_u6_s9_end:
|
|
|
|
; bbit0.t limm,u6,s9
|
|
.set bbit0_t_limm_u6_s9_target, @.Lbbit_target
|
|
.set bbit0_t_limm_u6_s9_has_delay_slot, 0
|
|
.set bbit0_t_limm_u6_s9_cc, 0
|
|
bbit0_t_limm_u6_s9_start:
|
|
bbit0.t limm_value,u6_value,@.Lbbit_target
|
|
bbit0_t_limm_u6_s9_end:
|
|
|
|
; bbit1.nt b,c,s9
|
|
.set bbit1_nt_b_c_s9_target, @.Lbbit_target
|
|
.set bbit1_nt_b_c_s9_has_delay_slot, 0
|
|
.set bbit1_nt_b_c_s9_cc, 0
|
|
bbit1_nt_b_c_s9_start:
|
|
bbit1.nt r4,r5,@.Lbbit_target
|
|
bbit1_nt_b_c_s9_end:
|
|
|
|
; bbit1.d.nt b,c,s9
|
|
.set bbit1_d_nt_b_c_s9_target, @.Lbbit_target
|
|
.set bbit1_d_nt_b_c_s9_has_delay_slot, 1
|
|
.set bbit1_d_nt_b_c_s9_cc, 0
|
|
bbit1_d_nt_b_c_s9_start:
|
|
bbit1.d.nt r4,r5,@.Lbbit_target
|
|
bbit1_d_nt_b_c_s9_end:
|
|
nop_s
|
|
|
|
; bbit1.t b,c,s9
|
|
.set bbit1_t_b_c_s9_target, @.Lbbit_target
|
|
.set bbit1_t_b_c_s9_has_delay_slot, 0
|
|
.set bbit1_t_b_c_s9_cc, 0
|
|
bbit1_t_b_c_s9_start:
|
|
bbit1.t r4,r5,@.Lbbit_target
|
|
bbit1_t_b_c_s9_end:
|
|
|
|
; bbit1.d.t b,c,s9
|
|
.set bbit1_d_t_b_c_s9_target, @.Lbbit_target
|
|
.set bbit1_d_t_b_c_s9_has_delay_slot, 1
|
|
.set bbit1_d_t_b_c_s9_cc, 0
|
|
bbit1_d_t_b_c_s9_start:
|
|
bbit1.d.t r4,r5,@.Lbbit_target
|
|
bbit1_d_t_b_c_s9_end:
|
|
nop_s
|
|
|
|
; bbit1.nt b,u6,s9
|
|
.set bbit1_nt_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit1_nt_b_u6_s9_has_delay_slot, 0
|
|
.set bbit1_nt_b_u6_s9_cc, 0
|
|
bbit1_nt_b_u6_s9_start:
|
|
bbit1.nt r4,u6_value,@.Lbbit_target
|
|
bbit1_nt_b_u6_s9_end:
|
|
|
|
; bbit1.d.nt b,u6,s9
|
|
.set bbit1_d_nt_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit1_d_nt_b_u6_s9_has_delay_slot, 1
|
|
.set bbit1_d_nt_b_u6_s9_cc, 0
|
|
bbit1_d_nt_b_u6_s9_start:
|
|
bbit1.d.nt r4,u6_value,@.Lbbit_target
|
|
bbit1_d_nt_b_u6_s9_end:
|
|
nop_s
|
|
|
|
; bbit1.nt b,u6,s9
|
|
.set bbit1_t_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit1_t_b_u6_s9_has_delay_slot, 0
|
|
.set bbit1_t_b_u6_s9_cc, 0
|
|
bbit1_t_b_u6_s9_start:
|
|
bbit1.t r4,u6_value,@.Lbbit_target
|
|
bbit1_t_b_u6_s9_end:
|
|
|
|
; bbit1.d.nt b,u6,s9
|
|
.set bbit1_d_t_b_u6_s9_target, @.Lbbit_target
|
|
.set bbit1_d_t_b_u6_s9_has_delay_slot, 1
|
|
.set bbit1_d_t_b_u6_s9_cc, 0
|
|
bbit1_d_t_b_u6_s9_start:
|
|
bbit1.d.t r4,u6_value,@.Lbbit_target
|
|
bbit1_d_t_b_u6_s9_end:
|
|
nop_s
|
|
|
|
; bbit1.nt b,limm,s9
|
|
.set bbit1_nt_b_limm_s9_target, @.Lbbit_target
|
|
.set bbit1_nt_b_limm_s9_has_delay_slot, 0
|
|
.set bbit1_nt_b_limm_s9_cc, 0
|
|
bbit1_nt_b_limm_s9_start:
|
|
bbit1.nt r4,limm_value,@.Lbbit_target
|
|
bbit1_nt_b_limm_s9_end:
|
|
|
|
; bbit1.t b,limm,s9
|
|
.set bbit1_t_b_limm_s9_target, @.Lbbit_target
|
|
.set bbit1_t_b_limm_s9_has_delay_slot, 0
|
|
.set bbit1_t_b_limm_s9_cc, 0
|
|
bbit1_t_b_limm_s9_start:
|
|
bbit1.t r4,limm_value,@.Lbbit_target
|
|
bbit1_t_b_limm_s9_end:
|
|
|
|
; bbit1.nt limm,c,s9
|
|
.set bbit1_nt_limm_c_s9_target, @.Lbbit_target
|
|
.set bbit1_nt_limm_c_s9_has_delay_slot, 0
|
|
.set bbit1_nt_limm_c_s9_cc, 0
|
|
bbit1_nt_limm_c_s9_start:
|
|
bbit1.nt limm_value,r4,@.Lbbit_target
|
|
bbit1_nt_limm_c_s9_end:
|
|
|
|
; bbit1.t limm,c,s9
|
|
.set bbit1_t_limm_c_s9_target, @.Lbbit_target
|
|
.set bbit1_t_limm_c_s9_has_delay_slot, 0
|
|
.set bbit1_t_limm_c_s9_cc, 0
|
|
bbit1_t_limm_c_s9_start:
|
|
bbit1.t limm_value,r4,@.Lbbit_target
|
|
bbit1_t_limm_c_s9_end:
|
|
|
|
; bbit1.nt limm,u6,s9
|
|
.set bbit1_nt_limm_u6_s9_target, @.Lbbit_target
|
|
.set bbit1_nt_limm_u6_s9_has_delay_slot, 0
|
|
.set bbit1_nt_limm_u6_s9_cc, 0
|
|
bbit1_nt_limm_u6_s9_start:
|
|
bbit1.nt limm_value,u6_value,@.Lbbit_target
|
|
bbit1_nt_limm_u6_s9_end:
|
|
|
|
; bbit1.t limm,u6,s9
|
|
.set bbit1_t_limm_u6_s9_target, @.Lbbit_target
|
|
.set bbit1_t_limm_u6_s9_has_delay_slot, 0
|
|
.set bbit1_t_limm_u6_s9_cc, 0
|
|
bbit1_t_limm_u6_s9_start:
|
|
bbit1.t limm_value,u6_value,@.Lbbit_target
|
|
bbit1_t_limm_u6_s9_end:
|
|
#endif /* TEST_BBIT */
|
|
|
|
#ifdef TEST_BCC
|
|
.Lbcc_target:
|
|
; bcc s21
|
|
.set bcc_s21_target, @.Lbcc_target
|
|
.set bcc_s21_has_delay_slot, 0
|
|
.set bcc_s21_cc, 1
|
|
bcc_s21_start:
|
|
; beq @bcc_s21_target
|
|
beq @.Lbcc_target
|
|
bcc_s21_end:
|
|
|
|
; bcc.d s21
|
|
.set bcc_d_s21_target, @.Lbcc_target
|
|
.set bcc_d_s21_has_delay_slot, 1
|
|
.set bcc_d_s21_cc, 1
|
|
bcc_d_s21_start:
|
|
beq.d @bcc_d_s21_target
|
|
bcc_d_s21_end:
|
|
nop_s
|
|
|
|
.Lbcc_s_target:
|
|
; beq_s s10
|
|
.set beq_s_s10_target, @.Lbcc_s_target
|
|
.set beq_s_s10_has_delay_slot, 0
|
|
.set beq_s_s10_cc, 1
|
|
beq_s_s10_start:
|
|
# beq_s.d @beq_s_s10_target
|
|
beq_s @.Lbcc_s_target
|
|
beq_s_s10_end:
|
|
|
|
; bne_s s10
|
|
.set bne_s_s10_target, @.Lbcc_s_target
|
|
.set bne_s_s10_has_delay_slot, 0
|
|
.set bne_s_s10_cc, 2
|
|
bne_s_s10_start:
|
|
bne_s @bne_s_s10_target
|
|
bne_s_s10_end:
|
|
|
|
; bgt_s s7
|
|
.set bgt_s_s7_target, @.Lbcc_s_target
|
|
.set bgt_s_s7_has_delay_slot, 0
|
|
.set bgt_s_s7_cc, 0x9
|
|
bgt_s_s7_start:
|
|
bgt_s @bgt_s_s7_target
|
|
bgt_s_s7_end:
|
|
|
|
; bge_s s7
|
|
.set bge_s_s7_target, @.Lbcc_s_target
|
|
.set bge_s_s7_has_delay_slot, 0
|
|
.set bge_s_s7_cc, 0xA
|
|
bge_s_s7_start:
|
|
bge_s @bge_s_s7_target
|
|
bge_s_s7_end:
|
|
|
|
; blt_s s7
|
|
.set blt_s_s7_target, @.Lbcc_s_target
|
|
.set blt_s_s7_has_delay_slot, 0
|
|
.set blt_s_s7_cc, 0xB
|
|
blt_s_s7_start:
|
|
blt_s @blt_s_s7_target
|
|
blt_s_s7_end:
|
|
|
|
; ble_s s7
|
|
.set ble_s_s7_target, @.Lbcc_s_target
|
|
.set ble_s_s7_has_delay_slot, 0
|
|
.set ble_s_s7_cc, 0xC
|
|
ble_s_s7_start:
|
|
ble_s @ble_s_s7_target
|
|
ble_s_s7_end:
|
|
|
|
; bhi_s s7
|
|
.set bhi_s_s7_target, @.Lbcc_s_target
|
|
.set bhi_s_s7_has_delay_slot, 0
|
|
.set bhi_s_s7_cc, 0xD
|
|
bhi_s_s7_start:
|
|
bhi_s @bhi_s_s7_target
|
|
bhi_s_s7_end:
|
|
|
|
; bhs_s s7
|
|
.set bhs_s_s7_target, @.Lbcc_s_target
|
|
.set bhs_s_s7_has_delay_slot, 0
|
|
.set bhs_s_s7_cc, 0x6
|
|
bhs_s_s7_start:
|
|
bhs_s @bhs_s_s7_target
|
|
bhs_s_s7_end:
|
|
|
|
; blo_s s7
|
|
.set blo_s_s7_target, @.Lbcc_s_target
|
|
.set blo_s_s7_has_delay_slot, 0
|
|
.set blo_s_s7_cc, 0x5
|
|
blo_s_s7_start:
|
|
blo_s @blo_s_s7_target
|
|
blo_s_s7_end:
|
|
|
|
; bls_s s7
|
|
.set bls_s_s7_target, @.Lbcc_s_target
|
|
.set bls_s_s7_has_delay_slot, 0
|
|
.set bls_s_s7_cc, 0xE
|
|
bls_s_s7_start:
|
|
bls_s @bls_s_s7_target
|
|
bls_s_s7_end:
|
|
#endif /* TEST_BCC */
|
|
|
|
#ifdef TEST_BI
|
|
; bi [c]
|
|
.set bi_c_target, @bi_c_end + (@r7_value << 2)
|
|
.set bi_c_has_delay_slot, 0
|
|
.set bi_c_cc, 0
|
|
bi_c_start:
|
|
bi [r7]
|
|
bi_c_end:
|
|
|
|
; bih [c]
|
|
.set bih_c_target, @bih_c_end + (@r7_value << 1)
|
|
.set bih_c_has_delay_slot, 0
|
|
.set bih_c_cc, 0
|
|
bih_c_start:
|
|
bih [r7]
|
|
bih_c_end:
|
|
#endif /* TEST_BI */
|
|
|
|
#ifdef TEST_BL
|
|
.Lbl_target:
|
|
; bl s25
|
|
.set bl_s25_target, @.Lbl_target
|
|
.set bl_s25_has_delay_slot, 0
|
|
.set bl_s25_cc, 0
|
|
bl_s25_start:
|
|
bl @bl_s25_target
|
|
bl_s25_end:
|
|
|
|
; bl.d s25
|
|
.set bl_d_s25_target, @.Lbl_target
|
|
.set bl_d_s25_has_delay_slot, 1
|
|
.set bl_d_s25_cc, 0
|
|
bl_d_s25_start:
|
|
bl.d @bl_d_s25_target
|
|
bl_d_s25_end:
|
|
nop_s
|
|
|
|
; bl_s s13
|
|
.set bl_s_s13_target, @.Lbl_target
|
|
.set bl_s_s13_has_delay_slot, 0
|
|
.set bl_s_s13_cc, 0
|
|
bl_s_s13_start:
|
|
bl_s @bl_s_s13_target
|
|
bl_s_s13_end:
|
|
|
|
; blcc s21
|
|
.set blcc_s21_target, @.Lbl_target
|
|
.set blcc_s21_has_delay_slot, 0
|
|
.set blcc_s21_cc, 1
|
|
blcc_s21_start:
|
|
bleq @blcc_s21_target
|
|
blcc_s21_end:
|
|
|
|
; blcc.d s21
|
|
.set blcc_d_s21_target, @.Lbl_target
|
|
.set blcc_d_s21_has_delay_slot, 1
|
|
.set blcc_d_s21_cc, 2
|
|
blcc_d_s21_start:
|
|
blnz.d @blcc_d_s21_target
|
|
blcc_d_s21_end:
|
|
nop_s
|
|
#endif /* TEST_BL */
|
|
|
|
#ifdef TEST_BRCC
|
|
.Lbrcc_target:
|
|
; breq.nt b,c,s9
|
|
.set breq_nt_b_c_s9_target, @.Lbrcc_target
|
|
.set breq_nt_b_c_s9_has_delay_slot, 0
|
|
.set breq_nt_b_c_s9_cc, 1
|
|
breq_nt_b_c_s9_start:
|
|
breq.nt r4,r5,@.Lbrcc_target
|
|
breq_nt_b_c_s9_end:
|
|
|
|
; breq.d.nt b,c,s9
|
|
.set breq_d_nt_b_c_s9_target, @.Lbrcc_target
|
|
.set breq_d_nt_b_c_s9_has_delay_slot, 1
|
|
.set breq_d_nt_b_c_s9_cc, 1
|
|
breq_d_nt_b_c_s9_start:
|
|
breq.d.nt r4,r5,@.Lbrcc_target
|
|
breq_d_nt_b_c_s9_end:
|
|
nop_s
|
|
|
|
; breq.t b,c,s9
|
|
.set breq_t_b_c_s9_target, @.Lbrcc_target
|
|
.set breq_t_b_c_s9_has_delay_slot, 0
|
|
.set breq_t_b_c_s9_cc, 1
|
|
breq_t_b_c_s9_start:
|
|
breq.t r4,r5,@.Lbrcc_target
|
|
breq_t_b_c_s9_end:
|
|
|
|
; breq.d.t b,c,s9
|
|
.set breq_d_t_b_c_s9_target, @.Lbrcc_target
|
|
.set breq_d_t_b_c_s9_has_delay_slot, 1
|
|
.set breq_d_t_b_c_s9_cc, 1
|
|
breq_d_t_b_c_s9_start:
|
|
breq.d.t r4,r5,@.Lbrcc_target
|
|
breq_d_t_b_c_s9_end:
|
|
nop_s
|
|
|
|
; breq.nt b,u6,s9
|
|
.set breq_nt_b_u6_s9_target, @.Lbrcc_target
|
|
.set breq_nt_b_u6_s9_has_delay_slot, 0
|
|
.set breq_nt_b_u6_s9_cc, 1
|
|
breq_nt_b_u6_s9_start:
|
|
breq.nt r4,u6_value,@.Lbrcc_target
|
|
breq_nt_b_u6_s9_end:
|
|
|
|
; breq.d.nt b,u6,s9
|
|
.set breq_d_nt_b_u6_s9_target, @.Lbrcc_target
|
|
.set breq_d_nt_b_u6_s9_has_delay_slot, 1
|
|
.set breq_d_nt_b_u6_s9_cc, 1
|
|
breq_d_nt_b_u6_s9_start:
|
|
breq.d.nt r4,u6_value,@.Lbrcc_target
|
|
breq_d_nt_b_u6_s9_end:
|
|
nop_s
|
|
|
|
; breq.nt b,u6,s9
|
|
.set breq_t_b_u6_s9_target, @.Lbrcc_target
|
|
.set breq_t_b_u6_s9_has_delay_slot, 0
|
|
.set breq_t_b_u6_s9_cc, 1
|
|
breq_t_b_u6_s9_start:
|
|
breq.t r4,u6_value,@.Lbrcc_target
|
|
breq_t_b_u6_s9_end:
|
|
|
|
; breq.d.nt b,u6,s9
|
|
.set breq_d_t_b_u6_s9_target, @.Lbrcc_target
|
|
.set breq_d_t_b_u6_s9_has_delay_slot, 1
|
|
.set breq_d_t_b_u6_s9_cc, 1
|
|
breq_d_t_b_u6_s9_start:
|
|
breq.d.t r4,u6_value,@.Lbrcc_target
|
|
breq_d_t_b_u6_s9_end:
|
|
nop_s
|
|
|
|
; breq.nt b,limm,s9
|
|
.set breq_nt_b_limm_s9_target, @.Lbrcc_target
|
|
.set breq_nt_b_limm_s9_has_delay_slot, 0
|
|
.set breq_nt_b_limm_s9_cc, 1
|
|
breq_nt_b_limm_s9_start:
|
|
breq.nt r4,limm_value,@.Lbrcc_target
|
|
breq_nt_b_limm_s9_end:
|
|
|
|
; breq.t b,limm,s9
|
|
.set breq_t_b_limm_s9_target, @.Lbrcc_target
|
|
.set breq_t_b_limm_s9_has_delay_slot, 0
|
|
.set breq_t_b_limm_s9_cc, 1
|
|
breq_t_b_limm_s9_start:
|
|
breq.t r4,limm_value,@.Lbrcc_target
|
|
breq_t_b_limm_s9_end:
|
|
|
|
; breq.nt limm,c,s9
|
|
.set breq_nt_limm_c_s9_target, @.Lbrcc_target
|
|
.set breq_nt_limm_c_s9_has_delay_slot, 0
|
|
.set breq_nt_limm_c_s9_cc, 1
|
|
breq_nt_limm_c_s9_start:
|
|
breq.nt limm_value,r4,@.Lbrcc_target
|
|
breq_nt_limm_c_s9_end:
|
|
|
|
; breq.t limm,c,s9
|
|
.set breq_t_limm_c_s9_target, @.Lbrcc_target
|
|
.set breq_t_limm_c_s9_has_delay_slot, 0
|
|
.set breq_t_limm_c_s9_cc, 1
|
|
breq_t_limm_c_s9_start:
|
|
breq.t limm_value,r4,@.Lbrcc_target
|
|
breq_t_limm_c_s9_end:
|
|
|
|
; breq.nt limm,u6,s9
|
|
.set breq_nt_limm_u6_s9_target, @.Lbrcc_target
|
|
.set breq_nt_limm_u6_s9_has_delay_slot, 0
|
|
.set breq_nt_limm_u6_s9_cc, 1
|
|
breq_nt_limm_u6_s9_start:
|
|
breq.nt limm_value,u6_value,@.Lbrcc_target
|
|
breq_nt_limm_u6_s9_end:
|
|
|
|
; breq.t limm,u6,s9
|
|
.set breq_t_limm_u6_s9_target, @.Lbrcc_target
|
|
.set breq_t_limm_u6_s9_has_delay_slot, 0
|
|
.set breq_t_limm_u6_s9_cc, 1
|
|
breq_t_limm_u6_s9_start:
|
|
breq.t limm_value,u6_value,@.Lbrcc_target
|
|
breq_t_limm_u6_s9_end:
|
|
|
|
; brne_s b,0,s8
|
|
.set brne_s_b_0_s8_target, @.Lbrcc_target
|
|
.set brne_s_b_0_s8_has_delay_slot, 0
|
|
.set brne_s_b_0_s8_cc, 1
|
|
brne_s_b_0_s8_start:
|
|
brne r12,0,@.Lbrcc_target
|
|
brne_s_b_0_s8_end:
|
|
|
|
; breq_s b,0,s8
|
|
.set breq_s_b_0_s8_target, @.Lbrcc_target
|
|
.set breq_s_b_0_s8_has_delay_slot, 0
|
|
.set breq_s_b_0_s8_cc, 1
|
|
breq_s_b_0_s8_start:
|
|
breq r12,0,@.Lbrcc_target
|
|
breq_s_b_0_s8_end:
|
|
#endif /* TEST_BRCC */
|
|
|
|
#ifdef TEST_JLI
|
|
; jli_s u10
|
|
.set jli_s_u10_target, @jli_target
|
|
.set jli_s_u10_has_delay_slot, 0
|
|
.set jli_s_u10_cc, 0
|
|
jli_s_u10_start:
|
|
jli_s jli_offset
|
|
jli_s_u10_end:
|
|
#endif
|
|
|
|
#ifdef TEST_LEAVE_S
|
|
; leave_s
|
|
.set leave_s_target, @blink_value
|
|
.set leave_s_has_delay_slot, 0
|
|
.set leave_s_cc, 0
|
|
leave_s_start:
|
|
; leave_s [r13-gp,fp,blink,pcl]
|
|
leave_s (14 + 16 + 32 + 64)
|
|
leave_s_end:
|
|
#endif
|
|
|
|
#ifdef TEST_LPCC
|
|
; lpcc
|
|
.set lpcc_u7_target, @.Llpcc_end
|
|
.set lpcc_u7_has_delay_slot, 0
|
|
.set lpcc_u7_cc, 1
|
|
lpcc_u7_start:
|
|
lpeq @lpcc_u7_target
|
|
lpcc_u7_end:
|
|
nop
|
|
nop
|
|
.Llpcc_end:
|
|
#endif
|
|
|
|
.Lend:
|
|
|