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binutils-gdb/opcodes
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H.J. Lu 5db04b0965 Support AMD64/Intel ISAs in assembler/disassembler 
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode.  AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.

This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler.  The most permissive
ISA, which is AMD64, is the default.

GDB can add an option, similar to

(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".

to select which ISA to disassemble.

binutils/

	PR binutis/18386
	* doc/binutils.texi: Document -Mamd64 and -Mintel64.

gas/

	PR binutis/18386
	* config/tc-i386.c (OPTION_MAMD64): New.
	(OPTION_MINTEL64): Likewise.
	(md_longopts): Add -mamd64 and -mintel64.
	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
	(md_show_usage): Add -mamd64 and -mintel64.
	* doc/c-i386.texi: Document -mamd64 and -mintel64.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch-2.d: New file.
	* gas/i386/x86-64-branch-2.s: Likewise.
	* gas/i386/x86-64-branch-3.l: Likewise.
	* gas/i386/x86-64-branch-3.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
	objdump for tlspic.dd and tlsgdesc.dd.

opcodes/

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-05-15 09:48:10 -07:00
..
po Updated translations for various binutils components. 2015-04-29 16:26:14 +01:00
.gitignore
aarch64-asm-2.c [AARCH64] Remove Load/Store register (unscaled immediate) alias. 2015-03-10 11:27:56 +00:00
aarch64-asm.c
aarch64-asm.h
aarch64-dis-2.c [AARCH64] Remove Load/Store register (unscaled immediate) alias. 2015-03-10 11:27:56 +00:00
aarch64-dis.c
aarch64-dis.h
aarch64-gen.c
aarch64-opc-2.c [AARCH64] Remove Load/Store register (unscaled immediate) alias. 2015-03-10 11:27:56 +00:00
aarch64-opc.c
aarch64-opc.h
aarch64-tbl.h [AARCH64] Remove Load/Store register (unscaled immediate) alias. 2015-03-10 11:27:56 +00:00
aclocal.m4
alpha-dis.c
alpha-opc.c
arc-dis.c
arc-dis.h
arc-ext.c
arc-ext.h
arc-opc.c
arm-dis.c [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2 2015-04-15 17:44:03 +01:00
avr-dis.c
bfin-dis.c
cgen-asm.c
cgen-asm.in
cgen-bitset.c
cgen-dis.c
cgen-dis.in
cgen-ibld.in
cgen-opc.c
cgen.sh
ChangeLog Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-9297
ChangeLog-9899
config.in
configure Add Intel MCU support to opcodes 2015-05-11 10:48:21 -07:00
configure.ac Add Intel MCU support to opcodes 2015-05-11 10:48:21 -07:00
configure.com
cr16-dis.c
cr16-opc.c
cris-dis.c
cris-opc.c
crx-dis.c
crx-opc.c
d10v-dis.c
d10v-opc.c opcodes: d10v: fix old style prototype 2015-03-30 02:20:22 -04:00
d30v-dis.c
d30v-opc.c
dep-in.sed
dis-buf.c
dis-init.c
disassemble.c Add Intel MCU support to opcodes 2015-05-11 10:48:21 -07:00
dlx-dis.c
epiphany-asm.c
epiphany-desc.c
epiphany-desc.h
epiphany-dis.c
epiphany-ibld.c
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
fr30-dis.c
fr30-ibld.c
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c
frv-desc.h
frv-dis.c
frv-ibld.c
frv-opc.c
frv-opc.h
ft32-dis.c
ft32-opc.c
h8300-dis.c
h8500-dis.c
h8500-opc.h
hppa-dis.c
i370-dis.c
i370-opc.c
i386-dis-evex.h x86: disambiguate disassembly of certain AVX512 insns 2015-04-23 16:42:40 +02:00
i386-dis.c Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
i386-gen.c Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
i386-init.h Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
i386-opc.c
i386-opc.h Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
i386-opc.tbl Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
i386-reg.tbl
i386-tbl.h Support AMD64/Intel ISAs in assembler/disassembler 2015-05-15 09:48:10 -07:00
i860-dis.c
i960-dis.c
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c
ip2k-desc.h
ip2k-dis.c
ip2k-ibld.c
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c
iq2000-desc.h
iq2000-dis.c
iq2000-ibld.c
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c
lm32-desc.h
lm32-dis.c
lm32-ibld.c
lm32-opc.c
lm32-opc.h
lm32-opinst.c
m32c-asm.c
m32c-desc.c
m32c-desc.h
m32c-dis.c
m32c-ibld.c
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c
m32r-desc.h
m32r-dis.c
m32r-ibld.c
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c
m88k-dis.c
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
MAINTAINERS
Makefile.am
Makefile.in Regenerate opcodes/Makefile.in 2015-03-29 07:37:50 -07:00
makefile.vms
mcore-dis.c
mcore-opc.h
mep-asm.c
mep-desc.c
mep-desc.h
mep-dis.c
mep-ibld.c
mep-opc.c
mep-opc.h
metag-dis.c
microblaze-dis.c
microblaze-dis.h
microblaze-opc.h
microblaze-opcm.h
micromips-opc.c
mips16-opc.c
mips-dis.c
mips-formats.h
mips-opc.c MIPS: Fix constraint issues with the R6 beqc and bnec instructions 2015-03-13 23:01:34 +00:00
mmix-dis.c
mmix-opc.c
moxie-dis.c
moxie-opc.c
msp430-decode.c
msp430-decode.opc
msp430-dis.c
mt-asm.c
mt-desc.c
mt-desc.h
mt-dis.c
mt-ibld.c
mt-opc.c
mt-opc.h
nds32-asm.c
nds32-asm.h
nds32-dis.c
nds32-opc.h
nios2-dis.c
nios2-opc.c
ns32k-dis.c
opc2c.c
opintl.h
or1k-asm.c
or1k-desc.c
or1k-desc.h
or1k-dis.c
or1k-ibld.c
or1k-opc.c
or1k-opc.h
or1k-opinst.c
pdp11-dis.c
pdp11-opc.c
pj-dis.c
pj-opc.c
ppc-dis.c powerpc: Only initialise opcode indices once 2015-03-26 09:12:50 +11:00
ppc-opc.c Fix some PPC assembler errors. 2015-05-14 21:02:50 -05:00
rl78-decode.c Make RL78 disassembler and simulator respect ISA for mul/div 2015-04-30 15:25:49 -04:00
rl78-decode.opc Make RL78 disassembler and simulator respect ISA for mul/div 2015-04-30 15:25:49 -04:00
rl78-dis.c Make RL78 disassembler and simulator respect ISA for mul/div 2015-04-30 15:25:49 -04:00
rx-decode.c
rx-decode.opc
rx-dis.c
s390-dis.c
s390-mkopc.c
s390-opc.c S/390: Fixes for z13 instructions. 2015-04-27 10:29:16 +02:00
s390-opc.txt S/390: Fixes for z13 instructions. 2015-04-27 10:29:16 +02:00
score7-dis.c
score-dis.c
score-opc.h
sh64-dis.c
sh64-opc.c
sh64-opc.h
sh-dis.c
sh-opc.h [SH] Fix clrs, sets, pref insn arch memberships. 2015-02-25 21:26:59 +01:00
sparc-dis.c
sparc-opc.c
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h
tic4x-dis.c
tic6x-dis.c
tic30-dis.c
tic54x-dis.c
tic54x-opc.c
tic80-dis.c
tic80-opc.c
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c
v850-opc.c
vax-dis.c
visium-dis.c
visium-opc.c
w65-dis.c
w65-opc.h
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
xstormy16-dis.c
xstormy16-ibld.c
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c
z8k-dis.c
z8k-opc.h
z8kgen.c
z80-dis.c