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binutils-gdb/sim
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Mike Frysinger 7a9bd3b4e2 sim: erc32/m32c/rl78: add sim_memory_map stub for gdb 
These ports don't use the common sim core, so they weren't providing
a sim_memory_map for gdb, so they failed to link with the new memory
map logic added for the sim.  Add stubs to fix.
2021-02-06 12:15:34 -05:00
..
aarch64 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
arm sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
avr sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
bfin sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
bpf sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
common sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
cr16 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
cris sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
d10v sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
erc32 sim: erc32/m32c/rl78: add sim_memory_map stub for gdb 2021-02-06 12:15:34 -05:00
frv sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
ft32 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
h8300 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
igen sim: add ChangeLog entries for last commits 2021-02-06 12:07:08 -05:00
iq2000 sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
lm32 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
m32c sim: erc32/m32c/rl78: add sim_memory_map stub for gdb 2021-02-06 12:15:34 -05:00
m32r sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
m68hc11 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
mcore sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
microblaze sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
mips sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
mn10300 sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
moxie sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
msp430 sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
or1k sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
ppc sim: drop use of bfd/configure.host 2021-02-06 10:56:11 -05:00
pru sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
riscv sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
rl78 sim: erc32/m32c/rl78: add sim_memory_map stub for gdb 2021-02-06 12:15:34 -05:00
rx sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
sh sim: common: switch AC_CONFIG_HEADERS 2021-02-06 12:00:42 -05:00
testsuite sim: riscv: new port 2021-02-04 19:02:19 -05:00
v850 sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
.gitignore
ChangeLog sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00
configure sim: drop use of bfd/configure.host 2021-02-06 10:56:11 -05:00
configure.ac sim: drop use of bfd/configure.host 2021-02-06 10:56:11 -05:00
configure.tgt sim: riscv: new port 2021-02-04 19:02:19 -05:00
MAINTAINERS sim: readd myself as a maintainer 2021-01-29 22:11:45 -05:00
Makefile.in sim: common: change gennltvals helper to Python 2021-01-30 20:17:46 -05:00
README-HACKING sim: watchpoints: use common sim_pc_get 2021-02-06 12:12:51 -05:00