Jaydeep Patil 1c37b30945 sim/riscv: fix JALR instruction simulation ... Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>		2023-10-18 17:55:31 +01:00
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aarch64
arm
avr
bfin	Rename bfd_bread and bfd_bwrite	2023-08-09 08:48:09 +09:30
bpf	sim: bpf: remove negi, neg32i insns	2023-08-21 10:07:25 -07:00
common	Simplify definition of GUILE	2023-08-26 13:09:38 -06:00
cr16
cris	Placate -Wmissing-declarations in sim/cris	2023-08-19 12:26:21 -06:00
d10v
erc32
example-synacor
frv	sim regen	2023-08-19 12:41:32 +09:30
ft32
h8300
igen
iq2000	sim regen	2023-08-19 12:41:32 +09:30
lm32	sim regen	2023-08-19 12:41:32 +09:30
m4	sim --enable-cgen-maint	2023-08-19 12:41:32 +09:30
m32c
m32r	sim regen	2023-08-19 12:41:32 +09:30
m68hc11
mcore	[RFA] Fix for mcore simulator	2023-10-11 16:31:11 -06:00
microblaze
mips	sim: mips: fix printf string	2023-10-15 16:25:13 +05:45
mn10300
moxie
msp430
or1k	sim regen	2023-08-19 12:41:32 +09:30
ppc
pru
riscv	sim/riscv: fix JALR instruction simulation	2023-10-18 17:55:31 +01:00
rl78	Rename bfd_bread and bfd_bwrite	2023-08-09 08:48:09 +09:30
rx	Rename bfd_bread and bfd_bwrite	2023-08-09 08:48:09 +09:30
sh
testsuite	sim/riscv: fix JALR instruction simulation	2023-10-18 17:55:31 +01:00
v850
.gitignore
aclocal.m4
arch-subdir.mk.in
ChangeLog-2021
config.h.in
configure	sim --enable-cgen-maint	2023-08-19 12:41:32 +09:30
configure.ac
COPYING
gdbinit.in
MAINTAINERS
Makefile.am
Makefile.in	Simplify definition of GUILE	2023-08-26 13:09:38 -06:00
README-HACKING
semcrisv32f-switch.c	sim regen	2023-08-19 12:41:32 +09:30