mirror of
https://sourceware.org/git/binutils-gdb.git
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9239bbd3a6
bfd/ PR ld/20030 * elf32-arm.c (is_thumb2_vldm): Account for T1 (DP) encoding. (stm32l4xx_need_create_replacing_stub): Rename ambiguous nb_regs to nb_words. (create_instruction_vldmia): Add is_dp to disambiguate SP/DP encoding. (create_instruction_vldmdb): Likewise. (stm32l4xx_create_replacing_stub_vldm): is_dp detects DP encoding, uses it to re-encode. ld/ PR ld/20030 * testsuite/ld-arm/arm-elf.exp: Run new stm32l4xx-fix-vldm-dp tests. Fix misnamed stm32l4xx-fix-all. * testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s: New tests for multiple loads with DP registers. * testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d: New reference file. * testsuite/ld-arm/stm32l4xx-fix-vldm.s: Add missing comment. * testsuite/ld-arm/stm32l4xx-fix-all.s: Add tests for multiple loads with DP registers. * testsuite/ld-arm/stm32l4xx-fix-all.d: Update reference.
117 lines
3.6 KiB
Makefile
117 lines
3.6 KiB
Makefile
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.*: file format elf32-littlearm.*
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Disassembly of section \.text:
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00008000 <__stm32l4xx_veneer_0>:
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8000: e899 01fe ldmia\.w r9, {r1, r2, r3, r4, r5, r6, r7, r8}
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8004: f000 b86e b\.w 80e4 <__stm32l4xx_veneer_0_r>
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8008: f7f0 a000 udf\.w #0
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800c: f7f0 a000 udf\.w #0
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00008010 <__stm32l4xx_veneer_1>:
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8010: e8b9 01fe ldmia\.w r9!, {r1, r2, r3, r4, r5, r6, r7, r8}
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8014: f000 b868 b\.w 80e8 <__stm32l4xx_veneer_1_r>
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8018: f7f0 a000 udf\.w #0
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801c: f7f0 a000 udf\.w #0
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00008020 <__stm32l4xx_veneer_2>:
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8020: e919 01fe ldmdb r9, {r1, r2, r3, r4, r5, r6, r7, r8}
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8024: f000 b862 b\.w 80ec <__stm32l4xx_veneer_2_r>
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8028: f7f0 a000 udf\.w #0
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802c: f7f0 a000 udf\.w #0
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00008030 <__stm32l4xx_veneer_3>:
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8030: e939 01fe ldmdb r9!, {r1, r2, r3, r4, r5, r6, r7, r8}
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8034: f000 b85c b\.w 80f0 <__stm32l4xx_veneer_3_r>
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8038: f7f0 a000 udf\.w #0
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803c: f7f0 a000 udf\.w #0
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00008040 <__stm32l4xx_veneer_4>:
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8040: e8bd 01fe ldmia\.w sp!, {r1, r2, r3, r4, r5, r6, r7, r8}
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8044: f000 b856 b\.w 80f4 <__stm32l4xx_veneer_4_r>
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8048: f7f0 a000 udf\.w #0
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804c: f7f0 a000 udf\.w #0
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00008050 <__stm32l4xx_veneer_5>:
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8050: ecd9 0a08 vldmia r9, {s1-s8}
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8054: f000 b850 b\.w 80f8 <__stm32l4xx_veneer_5_r>
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8058: f7f0 a000 udf\.w #0
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805c: f7f0 a000 udf\.w #0
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8060: f7f0 a000 udf\.w #0
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8064: f7f0 a000 udf\.w #0
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00008068 <__stm32l4xx_veneer_6>:
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8068: ecf6 4a08 vldmia r6!, {s9-s16}
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806c: f000 b846 b\.w 80fc <__stm32l4xx_veneer_6_r>
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8070: f7f0 a000 udf\.w #0
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8074: f7f0 a000 udf\.w #0
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8078: f7f0 a000 udf\.w #0
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807c: f7f0 a000 udf\.w #0
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00008080 <__stm32l4xx_veneer_7>:
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8080: ecfd 0a08 vpop {s1-s8}
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8084: f000 b83c b\.w 8100 <__stm32l4xx_veneer_7_r>
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8088: f7f0 a000 udf\.w #0
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808c: f7f0 a000 udf\.w #0
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8090: f7f0 a000 udf\.w #0
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8094: f7f0 a000 udf\.w #0
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00008098 <__stm32l4xx_veneer_8>:
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8098: ec99 1b08 vldmia r9, {d1-d4}
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809c: f000 b832 b\.w 8104 <__stm32l4xx_veneer_8_r>
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80a0: f7f0 a000 udf\.w #0
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80a4: f7f0 a000 udf\.w #0
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80a8: f7f0 a000 udf\.w #0
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80ac: f7f0 a000 udf\.w #0
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000080b0 <__stm32l4xx_veneer_9>:
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80b0: ecb6 8b08 vldmia r6!, {d8-d11}
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80b4: f000 b828 b\.w 8108 <__stm32l4xx_veneer_9_r>
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80b8: f7f0 a000 udf\.w #0
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80bc: f7f0 a000 udf\.w #0
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80c0: f7f0 a000 udf\.w #0
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80c4: f7f0 a000 udf\.w #0
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000080c8 <__stm32l4xx_veneer_a>:
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80c8: ecbd 1b08 vpop {d1-d4}
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80cc: f000 b81e b\.w 810c <__stm32l4xx_veneer_a_r>
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80d0: f7f0 a000 udf\.w #0
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80d4: f7f0 a000 udf\.w #0
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80d8: f7f0 a000 udf\.w #0
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80dc: f7f0 a000 udf\.w #0
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000080e0 <_start>:
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80e0: f7ff bf8e b\.w 8000 <__stm32l4xx_veneer_0>
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000080e4 <__stm32l4xx_veneer_0_r>:
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80e4: f7ff bf94 b\.w 8010 <__stm32l4xx_veneer_1>
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000080e8 <__stm32l4xx_veneer_1_r>:
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80e8: f7ff bf9a b\.w 8020 <__stm32l4xx_veneer_2>
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000080ec <__stm32l4xx_veneer_2_r>:
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80ec: f7ff bfa0 b\.w 8030 <__stm32l4xx_veneer_3>
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000080f0 <__stm32l4xx_veneer_3_r>:
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80f0: f7ff bfa6 b\.w 8040 <__stm32l4xx_veneer_4>
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000080f4 <__stm32l4xx_veneer_4_r>:
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80f4: f7ff bfac b\.w 8050 <__stm32l4xx_veneer_5>
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000080f8 <__stm32l4xx_veneer_5_r>:
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80f8: f7ff bfb6 b\.w 8068 <__stm32l4xx_veneer_6>
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000080fc <__stm32l4xx_veneer_6_r>:
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80fc: f7ff bfc0 b\.w 8080 <__stm32l4xx_veneer_7>
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00008100 <__stm32l4xx_veneer_7_r>:
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8100: f7ff bfca b\.w 8098 <__stm32l4xx_veneer_8>
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00008104 <__stm32l4xx_veneer_8_r>:
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8104: f7ff bfd4 b\.w 80b0 <__stm32l4xx_veneer_9>
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00008108 <__stm32l4xx_veneer_9_r>:
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8108: f7ff bfde b\.w 80c8 <__stm32l4xx_veneer_a>
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