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5bc4f5ca15
When compiling we get the following warnings:
common/cgen-accfp.c: In function 'fixsfsi':
common/cgen-accfp.c:370:18: warning: pointer targets in passing argument 1 of 'sim_fpu_to32i' differ in signedness [-Wpointer-sign]
sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
^
common/cgen-accfp.c: In function 'fixdfsi':
common/cgen-accfp.c:381:18: warning: pointer targets in passing argument 1 of 'sim_fpu_to32i' differ in signedness [-Wpointer-sign]
sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
^
796 lines
13 KiB
C
796 lines
13 KiB
C
/* Accurate fp support for CGEN-based simulators.
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Copyright (C) 1999 Cygnus Solutions.
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This implemention assumes:
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typedef USI SF;
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typedef UDI DF;
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TODO:
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- lazy encoding/decoding
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- checking return code (say by callback)
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- proper rounding
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*/
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#include "sim-main.h"
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#include "sim-fpu.h"
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/* SF mode support */
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static SF
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addsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_add (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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subsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_sub (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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mulsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_mul (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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divsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_div (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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remsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_rem (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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negsf (CGEN_FPU* fpu, SF x)
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{
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sim_fpu op1;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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status = sim_fpu_neg (&ans, &op1);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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abssf (CGEN_FPU* fpu, SF x)
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{
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sim_fpu op1;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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status = sim_fpu_abs (&ans, &op1);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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sqrtsf (CGEN_FPU* fpu, SF x)
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{
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sim_fpu op1;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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status = sim_fpu_sqrt (&ans, &op1);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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invsf (CGEN_FPU* fpu, SF x)
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{
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sim_fpu op1;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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status = sim_fpu_inv (&ans, &op1);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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minsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_min (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SF
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maxsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_status status;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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status = sim_fpu_max (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static CGEN_FP_CMP
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cmpsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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if (sim_fpu_is_nan (&op1)
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|| sim_fpu_is_nan (&op2))
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return FP_CMP_NAN;
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if (x < y)
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return FP_CMP_LT;
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if (x > y)
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return FP_CMP_GT;
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return FP_CMP_EQ;
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}
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static int
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eqsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_eq (&op1, &op2);
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}
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static int
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nesf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_ne (&op1, &op2);
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}
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static int
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ltsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_lt (&op1, &op2);
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}
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static int
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lesf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_le (&op1, &op2);
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}
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static int
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gtsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_gt (&op1, &op2);
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}
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static int
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gesf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_ge (&op1, &op2);
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}
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static int
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unorderedsf (CGEN_FPU* fpu, SF x, SF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu_32to (&op1, x);
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sim_fpu_32to (&op2, y);
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return sim_fpu_is_nan (&op1) || sim_fpu_is_nan (&op2);
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}
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static DF
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fextsfdf (CGEN_FPU* fpu, int how UNUSED, SF x)
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{
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sim_fpu op1;
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unsigned64 res;
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sim_fpu_32to (&op1, x);
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sim_fpu_to64 (&res, &op1);
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return res;
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}
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static SF
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ftruncdfsf (CGEN_FPU* fpu, int how UNUSED, DF x)
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{
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sim_fpu op1;
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unsigned32 res;
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sim_fpu_64to (&op1, x);
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sim_fpu_to32 (&res, &op1);
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return res;
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}
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static SF
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floatsisf (CGEN_FPU* fpu, int how UNUSED, SI x)
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{
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_i32to (&ans, x, sim_fpu_round_near);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static DF
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floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x)
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{
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_i32to (&ans, x, sim_fpu_round_near);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static DF
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floatdidf (CGEN_FPU* fpu, int how UNUSED, DI x)
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{
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_i64to (&ans, x, sim_fpu_round_near);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static SF
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ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x)
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{
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sim_fpu ans;
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unsigned32 res;
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sim_fpu_u32to (&ans, x, sim_fpu_round_near);
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sim_fpu_to32 (&res, &ans);
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return res;
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}
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static SI
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fixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
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{
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sim_fpu op1;
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signed32 res;
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sim_fpu_32to (&op1, x);
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sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
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return res;
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}
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static SI
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fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x)
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{
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sim_fpu op1;
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signed32 res;
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sim_fpu_64to (&op1, x);
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sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
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return res;
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}
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static DI
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fixdfdi (CGEN_FPU* fpu, int how UNUSED, DF x)
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{
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sim_fpu op1;
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signed64 res;
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sim_fpu_64to (&op1, x);
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sim_fpu_to64i (&res, &op1, sim_fpu_round_near);
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return res;
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}
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static USI
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ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
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{
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sim_fpu op1;
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unsigned32 res;
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sim_fpu_32to (&op1, x);
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sim_fpu_to32u (&res, &op1, sim_fpu_round_near);
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return res;
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}
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/* DF mode support */
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static DF
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adddf (CGEN_FPU* fpu, DF x, DF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_status status;
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sim_fpu_64to (&op1, x);
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sim_fpu_64to (&op2, y);
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status = sim_fpu_add (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static DF
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subdf (CGEN_FPU* fpu, DF x, DF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_status status;
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sim_fpu_64to (&op1, x);
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sim_fpu_64to (&op2, y);
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status = sim_fpu_sub (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static DF
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muldf (CGEN_FPU* fpu, DF x, DF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_status status;
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sim_fpu_64to (&op1, x);
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sim_fpu_64to (&op2, y);
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status = sim_fpu_mul (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static DF
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divdf (CGEN_FPU* fpu, DF x, DF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_status status;
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sim_fpu_64to (&op1, x);
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sim_fpu_64to (&op2, y);
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status = sim_fpu_div (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static DF
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remdf (CGEN_FPU* fpu, DF x, DF y)
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{
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sim_fpu op1;
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sim_fpu op2;
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_status status;
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sim_fpu_64to (&op1, x);
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sim_fpu_64to (&op2, y);
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status = sim_fpu_rem (&ans, &op1, &op2);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to64(&res, &ans);
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return res;
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}
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static DF
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negdf (CGEN_FPU* fpu, DF x)
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{
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sim_fpu op1;
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sim_fpu ans;
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unsigned64 res;
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sim_fpu_status status;
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sim_fpu_64to (&op1, x);
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status = sim_fpu_neg (&ans, &op1);
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if (status != 0)
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(*fpu->ops->error) (fpu, status);
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sim_fpu_to64 (&res, &ans);
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return res;
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}
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static DF
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absdf (CGEN_FPU* fpu, DF x)
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{
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sim_fpu op1;
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sim_fpu ans;
|
||
unsigned64 res;
|
||
sim_fpu_status status;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
status = sim_fpu_abs (&ans, &op1);
|
||
if (status != 0)
|
||
(*fpu->ops->error) (fpu, status);
|
||
sim_fpu_to64 (&res, &ans);
|
||
|
||
return res;
|
||
}
|
||
|
||
static DF
|
||
sqrtdf (CGEN_FPU* fpu, DF x)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu ans;
|
||
unsigned64 res;
|
||
sim_fpu_status status;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
status = sim_fpu_sqrt (&ans, &op1);
|
||
if (status != 0)
|
||
(*fpu->ops->error) (fpu, status);
|
||
sim_fpu_to64 (&res, &ans);
|
||
|
||
return res;
|
||
}
|
||
|
||
static DF
|
||
invdf (CGEN_FPU* fpu, DF x)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu ans;
|
||
unsigned64 res;
|
||
sim_fpu_status status;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
status = sim_fpu_inv (&ans, &op1);
|
||
if (status != 0)
|
||
(*fpu->ops->error) (fpu, status);
|
||
sim_fpu_to64 (&res, &ans);
|
||
|
||
return res;
|
||
}
|
||
|
||
static DF
|
||
mindf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
sim_fpu ans;
|
||
unsigned64 res;
|
||
sim_fpu_status status;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
status = sim_fpu_min (&ans, &op1, &op2);
|
||
if (status != 0)
|
||
(*fpu->ops->error) (fpu, status);
|
||
sim_fpu_to64 (&res, &ans);
|
||
|
||
return res;
|
||
}
|
||
|
||
static DF
|
||
maxdf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
sim_fpu ans;
|
||
unsigned64 res;
|
||
sim_fpu_status status;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
status = sim_fpu_max (&ans, &op1, &op2);
|
||
if (status != 0)
|
||
(*fpu->ops->error) (fpu, status);
|
||
sim_fpu_to64 (&res, &ans);
|
||
|
||
return res;
|
||
}
|
||
|
||
static CGEN_FP_CMP
|
||
cmpdf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
|
||
if (sim_fpu_is_nan (&op1)
|
||
|| sim_fpu_is_nan (&op2))
|
||
return FP_CMP_NAN;
|
||
|
||
if (x < y)
|
||
return FP_CMP_LT;
|
||
if (x > y)
|
||
return FP_CMP_GT;
|
||
return FP_CMP_EQ;
|
||
}
|
||
|
||
static int
|
||
eqdf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_eq (&op1, &op2);
|
||
}
|
||
|
||
static int
|
||
nedf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_ne (&op1, &op2);
|
||
}
|
||
|
||
static int
|
||
ltdf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_lt (&op1, &op2);
|
||
}
|
||
|
||
static int
|
||
ledf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_le (&op1, &op2);
|
||
}
|
||
|
||
static int
|
||
gtdf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_gt (&op1, &op2);
|
||
}
|
||
|
||
static int
|
||
gedf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_ge (&op1, &op2);
|
||
}
|
||
|
||
static int
|
||
unordereddf (CGEN_FPU* fpu, DF x, DF y)
|
||
{
|
||
sim_fpu op1;
|
||
sim_fpu op2;
|
||
|
||
sim_fpu_64to (&op1, x);
|
||
sim_fpu_64to (&op2, y);
|
||
return sim_fpu_is_nan (&op1) || sim_fpu_is_nan (&op2);
|
||
}
|
||
|
||
/* Initialize FP_OPS to use accurate library. */
|
||
|
||
void
|
||
cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
|
||
{
|
||
CGEN_FP_OPS* o;
|
||
|
||
fpu->owner = cpu;
|
||
/* ??? small memory leak, not freed by sim_close */
|
||
fpu->ops = (CGEN_FP_OPS*) xmalloc (sizeof (CGEN_FP_OPS));
|
||
|
||
o = fpu->ops;
|
||
memset (o, 0, sizeof (*o));
|
||
|
||
o->error = error;
|
||
|
||
o->addsf = addsf;
|
||
o->subsf = subsf;
|
||
o->mulsf = mulsf;
|
||
o->divsf = divsf;
|
||
o->remsf = remsf;
|
||
o->negsf = negsf;
|
||
o->abssf = abssf;
|
||
o->sqrtsf = sqrtsf;
|
||
o->invsf = invsf;
|
||
o->minsf = minsf;
|
||
o->maxsf = maxsf;
|
||
o->cmpsf = cmpsf;
|
||
o->eqsf = eqsf;
|
||
o->nesf = nesf;
|
||
o->ltsf = ltsf;
|
||
o->lesf = lesf;
|
||
o->gtsf = gtsf;
|
||
o->gesf = gesf;
|
||
o->unorderedsf = unorderedsf;
|
||
|
||
o->adddf = adddf;
|
||
o->subdf = subdf;
|
||
o->muldf = muldf;
|
||
o->divdf = divdf;
|
||
o->remdf = remdf;
|
||
o->negdf = negdf;
|
||
o->absdf = absdf;
|
||
o->sqrtdf = sqrtdf;
|
||
o->invdf = invdf;
|
||
o->mindf = mindf;
|
||
o->maxdf = maxdf;
|
||
o->cmpdf = cmpdf;
|
||
o->eqdf = eqdf;
|
||
o->nedf = nedf;
|
||
o->ltdf = ltdf;
|
||
o->ledf = ledf;
|
||
o->gtdf = gtdf;
|
||
o->gedf = gedf;
|
||
o->unordereddf = unordereddf;
|
||
o->fextsfdf = fextsfdf;
|
||
o->ftruncdfsf = ftruncdfsf;
|
||
o->floatsisf = floatsisf;
|
||
o->floatsidf = floatsidf;
|
||
o->floatdidf = floatdidf;
|
||
o->ufloatsisf = ufloatsisf;
|
||
o->fixsfsi = fixsfsi;
|
||
o->fixdfsi = fixdfsi;
|
||
o->fixdfdi = fixdfdi;
|
||
o->ufixsfsi = ufixsfsi;
|
||
}
|