Jan Beulich 1673df3278 x86-64: correct mis-named X86_64_0D enumerator ... This is for major opcode 0E, so name it accordingly.		2020-03-13 09:57:10 +01:00
..
po
.gitignore
aarch64-asm-2.c	AArch64: Fix cfinv disassembly issues	2020-01-27 10:55:41 +00:00
aarch64-asm.c	Indent labels	2020-02-26 10:37:25 +10:30
aarch64-asm.h
aarch64-dis-2.c	AArch64: Fix cfinv disassembly issues	2020-01-27 10:55:41 +00:00
aarch64-dis.c	Indent labels	2020-02-26 10:37:25 +10:30
aarch64-dis.h
aarch64-gen.c	Indent labels	2020-02-26 10:37:25 +10:30
aarch64-opc-2.c	AArch64: Fix cfinv disassembly issues	2020-01-27 10:55:41 +00:00
aarch64-opc.c	Indent labels	2020-02-26 10:37:25 +10:30
aarch64-opc.h
aarch64-tbl.h	aarch64: Fix MOVPRFX markup for bf16 conversions	2020-01-31 13:22:46 +00:00
aclocal.m4
alpha-dis.c	Indent labels	2020-02-26 10:37:25 +10:30
alpha-opc.c
arc-dis.c
arc-dis.h
arc-ext-tbl.h
arc-ext.c
arc-ext.h
arc-fxi.h
arc-nps400-tbl.h
arc-opc.c
arc-regs.h	[ARC][committed] Update int_vector_base aux register.	2020-02-25 10:27:07 +02:00
arc-tbl.h
arm-dis.c	[binutils][arm] Implement Custom Datapath Extensions for MVE	2020-02-10 16:50:14 +00:00
avr-dis.c
bfin-dis.c
bpf-asm.c
bpf-desc.c
bpf-desc.h
bpf-dis.c
bpf-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
bpf-opc.c	cpu,opcodes,gas: fix neg and neg32 instructions in BPF	2020-01-30 13:59:04 +01:00
bpf-opc.h
cgen-asm.c
cgen-asm.in
cgen-bitset.c
cgen-dis.c
cgen-dis.in
cgen-ibld.in	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
cgen-opc.c
cgen.sh
ChangeLog	x86-64: correct mis-named X86_64_0D enumerator	2020-03-13 09:57:10 +01:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-2015
ChangeLog-2016
ChangeLog-2017
ChangeLog-2018
ChangeLog-2019
ChangeLog-9297
ChangeLog-9899
config.in
configure
configure.ac
configure.com
cr16-dis.c
cr16-opc.c
cris-dis.c
cris-opc.c
crx-dis.c
crx-opc.c
csky-dis.c
csky-opc.h
d10v-dis.c
d10v-opc.c
d30v-dis.c	ubsan: d30v: negation of -2147483648	2020-02-04 14:10:40 +10:30
d30v-opc.c
dep-in.sed
dis-buf.c
dis-init.c
disassemble.c
disassemble.h
dlx-dis.c
epiphany-asm.c
epiphany-desc.c
epiphany-desc.h
epiphany-dis.c
epiphany-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
fr30-dis.c
fr30-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c
frv-desc.h
frv-dis.c
frv-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
frv-opc.c
frv-opc.h
ft32-dis.c
ft32-opc.c
h8300-dis.c
hppa-dis.c
i386-dis-evex-len.h
i386-dis-evex-mod.h
i386-dis-evex-prefix.h	x86: replace EXxmm_mdq by EXVexWdqScalar	2020-01-31 14:29:18 +01:00
i386-dis-evex-reg.h
i386-dis-evex-w.h
i386-dis-evex.h
i386-dis.c	x86-64: correct mis-named X86_64_0D enumerator	2020-03-13 09:57:10 +01:00
i386-gen.c	x86: use template for SSE floating point comparison insns	2020-03-09 10:13:04 +01:00
i386-init.h	x86: support VMGEXIT	2020-03-04 08:58:13 +01:00
i386-opc.c
i386-opc.h	x86: drop Rex64 attribute	2020-03-06 08:52:12 +01:00
i386-opc.tbl	x86: use template for AVX512 integer comparison insns	2020-03-09 10:14:55 +01:00
i386-reg.tbl
i386-tbl.h	x86: use template for AVX512 integer comparison insns	2020-03-09 10:14:55 +01:00
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c
ip2k-desc.h
ip2k-dis.c
ip2k-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c
iq2000-desc.h
iq2000-dis.c
iq2000-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c
lm32-desc.h
lm32-dis.c
lm32-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
lm32-opc.c
lm32-opc.h
lm32-opinst.c
m32c-asm.c
m32c-desc.c
m32c-desc.h
m32c-dis.c
m32c-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c
m32r-desc.h
m32r-dis.c
m32r-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
MAINTAINERS
Makefile.am	x86: Also pass -P to $(CPP) when processing i386-opc.tbl	2020-03-09 08:23:46 -07:00
Makefile.in	x86: Also pass -P to $(CPP) when processing i386-opc.tbl	2020-03-09 08:23:46 -07:00
makefile.vms
mcore-dis.c
mcore-opc.h
mep-asm.c
mep-desc.c
mep-desc.h
mep-dis.c
mep-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
mep-opc.c
mep-opc.h
metag-dis.c
microblaze-dis.c
microblaze-dis.h
microblaze-opc.h
microblaze-opcm.h
micromips-opc.c
mips16-opc.c
mips-dis.c
mips-formats.h
mips-opc.c
mmix-dis.c
mmix-opc.c
moxie-dis.c
moxie-opc.c
msp430-decode.c
msp430-decode.opc
msp430-dis.c
mt-asm.c
mt-desc.c
mt-desc.h
mt-dis.c
mt-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
mt-opc.c
mt-opc.h
nds32-asm.c	Indent labels	2020-02-26 10:37:25 +10:30
nds32-asm.h
nds32-dis.c
nds32-opc.h
nfp-dis.c	Indent labels	2020-02-26 10:37:25 +10:30
nios2-dis.c
nios2-opc.c
ns32k-dis.c
opc2c.c
opintl.h
or1k-asm.c
or1k-desc.c
or1k-desc.h
or1k-dis.c
or1k-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
or1k-opc.c
or1k-opc.h
or1k-opinst.c
pdp11-dis.c
pdp11-opc.c
pj-dis.c
pj-opc.c
ppc-dis.c
ppc-opc.c
pru-dis.c
pru-opc.c
riscv-dis.c	RISC-V: Support the ISA-dependent CSR checking.	2020-02-20 16:49:09 -08:00
riscv-opc.c	RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.	2020-02-19 14:51:07 -08:00
rl78-decode.c
rl78-decode.opc
rl78-dis.c
rx-decode.c
rx-decode.opc
rx-dis.c
s12z-dis.c
s12z-opc.c
s12z-opc.h
s390-dis.c
s390-mkopc.c
s390-opc.c
s390-opc.txt
score7-dis.c
score-dis.c
score-opc.h
sh-dis.c
sh-opc.h
sparc-dis.c
sparc-opc.c
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h
tic4x-dis.c	ubsan: tic4x: left shift cannot be represented in type 'int'	2020-01-30 17:06:54 +10:30
tic6x-dis.c
tic30-dis.c
tic54x-dis.c
tic54x-opc.c
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c
v850-opc.c
vax-dis.c
visium-dis.c	Indent labels	2020-02-26 10:37:25 +10:30
visium-opc.c
wasm32-dis.c
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
xstormy16-dis.c
xstormy16-ibld.c	Ensure *valuep always written by extract_normal return	2020-02-11 12:14:01 +10:30
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c
z8k-dis.c
z8k-opc.h
z8kgen.c
z80-dis.c	The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble of this and LD (HL),IX instruction. Also it update testsuit.	2020-03-03 16:32:52 +00:00