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binutils-gdb/sim/example-synacor
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Mike Frysinger 4a21ad1e76 sim: enable common sim_cpu usage everywhere 
All ports should be migrated now.  Drop the SIM_HAVE_COMMON_SIM_CPU
knob and require it be used everywhere now.
2022-12-21 00:00:18 -05:00
..
ChangeLog-2021
interp.c sim: example-synacor: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
local.mk
Makefile.in
README
README.arch-spec
sim-main.c sim: example-synacor: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
sim-main.h sim: enable common sim_cpu usage everywhere 2022-12-21 00:00:18 -05:00

README 

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.