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6df01ab8ab
The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
305 lines
7.7 KiB
C
305 lines
7.7 KiB
C
/* OpenRISC exception, interrupts, syscall and trap support
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Copyright (C) 2017-2021 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#define WANT_CPU_OR1K32BF
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#define WANT_CPU
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#include "sim-main.h"
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#include "cgen-ops.h"
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/* Implement the sim invalid instruction function. This will set the error
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effective address to that of the invalid instruction then call the
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exception handler. */
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SEM_PC
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sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
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{
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SET_H_SYS_EEAR0 (cia);
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#ifdef WANT_CPU_OR1K32BF
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or1k32bf_exception (current_cpu, cia, EXCEPT_ILLEGAL);
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#endif
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return vpc;
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}
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/* Generate the appropriate OpenRISC fpu exception based on the status code from
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the sim fpu. */
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void
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or1k32bf_fpu_error (CGEN_FPU* fpu, int status)
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{
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SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner;
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/* If floating point exceptions are enabled. */
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if (GET_H_SYS_FPCSR_FPEE() != 0)
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{
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/* Set all of the status flag bits. */
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if (status
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& (sim_fpu_status_invalid_snan
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| sim_fpu_status_invalid_qnan
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| sim_fpu_status_invalid_isi
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| sim_fpu_status_invalid_idi
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| sim_fpu_status_invalid_zdz
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| sim_fpu_status_invalid_imz
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| sim_fpu_status_invalid_cvi
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| sim_fpu_status_invalid_cmp
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| sim_fpu_status_invalid_sqrt))
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SET_H_SYS_FPCSR_IVF (1);
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if (status & sim_fpu_status_invalid_snan)
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SET_H_SYS_FPCSR_SNF (1);
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if (status & sim_fpu_status_invalid_qnan)
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SET_H_SYS_FPCSR_QNF (1);
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if (status & sim_fpu_status_overflow)
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SET_H_SYS_FPCSR_OVF (1);
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if (status & sim_fpu_status_underflow)
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SET_H_SYS_FPCSR_UNF (1);
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if (status
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& (sim_fpu_status_invalid_isi
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| sim_fpu_status_invalid_idi))
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SET_H_SYS_FPCSR_INF (1);
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if (status & sim_fpu_status_invalid_div0)
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SET_H_SYS_FPCSR_DZF (1);
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if (status & sim_fpu_status_inexact)
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SET_H_SYS_FPCSR_IXF (1);
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/* If any of the exception bits were actually set. */
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if (GET_H_SYS_FPCSR()
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& (SPR_FIELD_MASK_SYS_FPCSR_IVF
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| SPR_FIELD_MASK_SYS_FPCSR_SNF
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| SPR_FIELD_MASK_SYS_FPCSR_QNF
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| SPR_FIELD_MASK_SYS_FPCSR_OVF
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| SPR_FIELD_MASK_SYS_FPCSR_UNF
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| SPR_FIELD_MASK_SYS_FPCSR_INF
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| SPR_FIELD_MASK_SYS_FPCSR_DZF
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| SPR_FIELD_MASK_SYS_FPCSR_IXF))
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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/* If the sim is running in fast mode, i.e. not profiling,
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per-instruction callbacks are not triggered which would allow
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us to track the PC. This means we cannot track which
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instruction caused the FPU error. */
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if (STATE_RUN_FAST_P (sd) == 1)
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sim_io_eprintf
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(sd, "WARNING: ignoring fpu error caught in fast mode.\n");
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else
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or1k32bf_exception (current_cpu, GET_H_SYS_PPC (), EXCEPT_FPE);
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}
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}
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}
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/* Implement the OpenRISC exception function. This is mostly used by the
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CGEN generated files. For example, this is used when handling a
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overflow exception during a multiplication instruction. */
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void
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or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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if (exnum == EXCEPT_TRAP)
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{
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/* Trap, used for breakpoints, sends control back to gdb breakpoint
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handling. */
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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}
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else
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{
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IADDR handler_pc;
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/* Calculate the exception program counter. */
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switch (exnum)
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{
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case EXCEPT_RESET:
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break;
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case EXCEPT_FPE:
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case EXCEPT_SYSCALL:
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SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0));
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break;
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case EXCEPT_BUSERR:
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case EXCEPT_ALIGN:
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case EXCEPT_ILLEGAL:
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case EXCEPT_RANGE:
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SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0));
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break;
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default:
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sim_io_error (sd, "unexpected exception 0x%x raised at PC 0x%08x",
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exnum, pc);
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break;
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}
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/* Store the current SR into ESR0. */
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SET_H_SYS_ESR0 (GET_H_SYS_SR ());
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/* Indicate in SR if the failed instruction is in delay slot or not. */
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SET_H_SYS_SR_DSX (current_cpu->delay_slot);
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current_cpu->next_delay_slot = 0;
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/* Jump program counter into handler. */
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handler_pc =
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(GET_H_SYS_SR_EPH () ? 0xf0000000 : 0x00000000) + (exnum << 8);
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sim_engine_restart (sd, current_cpu, NULL, handler_pc);
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}
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}
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/* Implement the return from exception instruction. This is used to return
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the CPU to its previous state from within an exception handler. */
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void
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or1k32bf_rfe (sim_cpu *current_cpu)
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{
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SET_H_SYS_SR (GET_H_SYS_ESR0 ());
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SET_H_SYS_SR_FO (1);
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current_cpu->next_delay_slot = 0;
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sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
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GET_H_SYS_EPCR0 ());
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}
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/* Implement the move from SPR instruction. This is used to read from the
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CPU's special purpose registers. */
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USI
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or1k32bf_mfspr (sim_cpu *current_cpu, USI addr)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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SI val;
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if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
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{
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sim_io_eprintf (sd, "WARNING: l.mfspr in user mode (SR 0x%x)\n",
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GET_H_SYS_SR ());
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return 0;
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}
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if (addr >= NUM_SPR)
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goto bad_address;
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val = GET_H_SPR (addr);
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switch (addr)
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{
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case SPR_ADDR (SYS, VR):
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case SPR_ADDR (SYS, UPR):
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case SPR_ADDR (SYS, CPUCFGR):
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case SPR_ADDR (SYS, SR):
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case SPR_ADDR (SYS, PPC):
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case SPR_ADDR (SYS, FPCSR):
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case SPR_ADDR (SYS, EPCR0):
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case SPR_ADDR (MAC, MACLO):
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case SPR_ADDR (MAC, MACHI):
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break;
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default:
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if (addr < SPR_ADDR (SYS, GPR0) || addr > SPR_ADDR (SYS, GPR511))
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goto bad_address;
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break;
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}
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return val;
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bad_address:
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sim_io_eprintf (sd, "WARNING: l.mfspr with invalid SPR address 0x%x\n", addr);
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return 0;
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}
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/* Implement the move to SPR instruction. This is used to write too the
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CPU's special purpose registers. */
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void
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or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
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{
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sim_io_eprintf
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(sd, "WARNING: l.mtspr with address 0x%x in user mode (SR 0x%x)\n",
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addr, GET_H_SYS_SR ());
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return;
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}
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if (addr >= NUM_SPR)
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goto bad_address;
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switch (addr)
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{
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case SPR_ADDR (SYS, FPCSR):
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case SPR_ADDR (SYS, EPCR0):
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case SPR_ADDR (SYS, ESR0):
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case SPR_ADDR (MAC, MACHI):
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case SPR_ADDR (MAC, MACLO):
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SET_H_SPR (addr, val);
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break;
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case SPR_ADDR (SYS, SR):
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SET_H_SPR (addr, val);
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SET_H_SYS_SR_FO (1);
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break;
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case SPR_ADDR (SYS, NPC):
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current_cpu->next_delay_slot = 0;
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sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, val);
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break;
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case SPR_ADDR (TICK, TTMR):
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/* Allow some registers to be silently cleared. */
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if (val != 0)
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sim_io_eprintf
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(sd, "WARNING: l.mtspr to SPR address 0x%x with invalid value 0x%x\n",
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addr, val);
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break;
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default:
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if (addr >= SPR_ADDR (SYS, GPR0) && addr <= SPR_ADDR (SYS, GPR511))
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SET_H_SPR (addr, val);
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else
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goto bad_address;
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break;
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}
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return;
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bad_address:
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sim_io_eprintf (sd, "WARNING: l.mtspr with invalid SPR address 0x%x\n", addr);
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}
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