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823 lines
15 KiB
Plaintext
823 lines
15 KiB
Plaintext
/* Copyright 2009-2021 Free Software Foundation, Inc.
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This file is part of the Xilinx MicroBlaze simulator.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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/*
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* MICROBLAZE Instruction Set Architecture
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*
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* INSTRUCTION(NAME,
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* OPCODE,
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* TYPE,
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* SEMANTICS)
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*
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*/
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INSTRUCTION(add,
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0x00,
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INST_TYPE_RD_RA_RB,
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CARRY = C_calc(RA, RB, 0);
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RD = RA + RB;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(rsub,
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0x01,
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INST_TYPE_RD_RA_RB,
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CARRY = C_calc(RB, ~RA, 1);
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RD = RB + ~RA + 1;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(addc,
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0x02,
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INST_TYPE_RD_RA_RB,
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CARRY = C_calc(RA, RB, C_rd);
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RD = RA + RB + C_rd;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(rsubc,
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0x03,
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INST_TYPE_RD_RA_RB,
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CARRY = C_calc(RB, ~RA, C_rd);
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RD = RB + ~RA + C_rd;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(addk,
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0x04,
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INST_TYPE_RD_RA_RB,
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RD = RA + RB;
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PC += INST_SIZE)
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INSTRUCTION(rsubk,
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0x05,
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INST_TYPE_RD_RA_RB,
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RD = RB + ~RA + 1;
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PC += INST_SIZE)
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INSTRUCTION(cmp,
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0x05,
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INST_TYPE_RD_RA_RB,
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{
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int tmp_reg = RB + ~RA + 1;
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if ((RB & 0x80000000) ^ (RA & 0x80000000)) {
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tmp_reg = ((tmp_reg & 0x7fffffff) | (RB & 0x80000000));
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}
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RD = tmp_reg;
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PC += INST_SIZE;
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})
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INSTRUCTION(cmpu,
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0x05,
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INST_TYPE_RD_RA_RB,
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{
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int tmp_reg = RB + ~RA + 1;
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if ((RB & 0x80000000) ^ (RA & 0x80000000)) {
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tmp_reg = ((tmp_reg & 0x7fffffff) | (RA & 0x80000000));
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}
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RD = tmp_reg;
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PC += INST_SIZE;
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})
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INSTRUCTION(addkc,
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0x06,
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INST_TYPE_RD_RA_RB,
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RD = RA + RB + C_rd;
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PC += INST_SIZE)
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INSTRUCTION(rsubkc,
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0x07,
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INST_TYPE_RD_RA_RB,
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RD = RB + ~RA + C_rd;
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PC += INST_SIZE)
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INSTRUCTION(addi,
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0x08,
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INST_TYPE_RD_RA_IMM,
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CARRY = C_calc(RA, IMM, 0);
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RD = RA + IMM;
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TRACE_REGISTER (cpu, "r%i = r%i + %i", rd, ra, IMM);
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(rsubi,
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0x09,
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INST_TYPE_RD_RA_IMM,
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CARRY = C_calc(IMM, ~RA, 1);
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RD = IMM + ~RA + 1;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(addic,
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0x0A,
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INST_TYPE_RD_RA_IMM,
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CARRY = C_calc(RA, IMM, C_rd);
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RD = RA + IMM + C_rd;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(rsubic,
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0x0B,
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INST_TYPE_RD_RA_IMM,
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CARRY = C_calc(IMM, ~RA, C_rd);
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RD = IMM + ~RA + C_rd;
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(addik,
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0x0C,
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INST_TYPE_RD_RA_IMM,
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RD = RA + IMM;
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PC += INST_SIZE)
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INSTRUCTION(rsubik,
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0x0D,
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INST_TYPE_RD_RA_IMM,
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RD = IMM + ~RA + 1;
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PC += INST_SIZE)
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INSTRUCTION(addikc,
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0x0E,
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INST_TYPE_RD_RA_IMM,
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RD = RA + IMM + C_rd;
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PC += INST_SIZE)
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INSTRUCTION(rsubikc,
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0x0F,
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INST_TYPE_RD_RA_IMM,
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RD = IMM + ~RA + C_rd;
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PC += INST_SIZE)
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INSTRUCTION(mul,
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0x10,
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INST_TYPE_RD_RA_RB,
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RD = RA * RB;
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PC += INST_SIZE)
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INSTRUCTION(bsrl,
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0x11,
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INST_TYPE_RD_RA_RB,
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RD = (uword)RA >> RB;
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PC += INST_SIZE)
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INSTRUCTION(bsra,
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0x11,
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INST_TYPE_RD_RA_RB,
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RD = (word)RA >> RB;
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PC += INST_SIZE)
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INSTRUCTION(bsll,
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0x11,
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INST_TYPE_RD_RA_RB,
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RD = (uword)RA << RB;
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PC += INST_SIZE)
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INSTRUCTION(idiv,
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0x12,
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INST_TYPE_RD_RA_RB,
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RD = (word) RB / (word) RA;
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PC += INST_SIZE)
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INSTRUCTION(idivu,
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0x12,
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INST_TYPE_RD_RA_RB,
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RD = (uword) RB / (uword) RA;
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PC += INST_SIZE)
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INSTRUCTION(muli,
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0x18,
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INST_TYPE_RD_RA_IMM,
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RD = RA * IMM;
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PC += INST_SIZE)
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INSTRUCTION(bsrli,
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0x19,
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INST_TYPE_RD_RA_IMM5,
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RD = (uword)RA >> (IMM & 0x1F);
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PC += INST_SIZE)
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INSTRUCTION(bsrai,
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0x19,
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INST_TYPE_RD_RA_IMM5,
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RD = (word)RA >> (IMM & 0x1F);
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PC += INST_SIZE)
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INSTRUCTION(bslli,
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0x19,
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INST_TYPE_RD_RA_IMM5,
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RD = (uword)RA << (IMM & 0x1F);
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PC += INST_SIZE)
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INSTRUCTION(get,
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0x1b,
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INST_TYPE_RD_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(put,
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0x1b,
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INST_TYPE_R1_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(nget,
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0x1b,
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INST_TYPE_RD_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(nput,
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0x1b,
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INST_TYPE_R1_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(cget,
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0x1b,
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INST_TYPE_RD_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(cput,
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0x1b,
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INST_TYPE_R1_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(ncget,
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0x1b,
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INST_TYPE_RD_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(ncput,
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0x1b,
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INST_TYPE_R1_IMM12,
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PC += INST_SIZE)
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INSTRUCTION(microblaze_or,
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0x20,
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INST_TYPE_RD_RA_RB,
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RD = RA | RB;
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PC += INST_SIZE)
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INSTRUCTION(microblaze_and,
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0x21,
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INST_TYPE_RD_RA_RB,
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RD = RA & RB;
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PC += INST_SIZE)
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INSTRUCTION(microblaze_xor,
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0x22,
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INST_TYPE_RD_RA_RB,
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RD = RA ^ RB;
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PC += INST_SIZE)
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INSTRUCTION(andn,
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0x23,
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INST_TYPE_RD_RA_RB,
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RD = RA & ~RB;
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PC += INST_SIZE)
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INSTRUCTION(sra,
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0x24,
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INST_TYPE_RD_RA,
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CARRY = (RA & 0x1);
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RD = (int) (RA >> 1);
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(src,
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0x24,
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INST_TYPE_RD_RA,
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CARRY = (RA & 0x1);
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RD = ((((int) (RA >> 1)) & 0x7FFFFFFF) | (uword)(C_rd << 31));
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(srl,
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0x24,
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INST_TYPE_RD_RA,
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CARRY = (RA & 0x1);
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RD = (uword) ((RA >> 1) & 0x7FFFFFFF);
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C_wr(CARRY);
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PC += INST_SIZE)
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INSTRUCTION(sext8,
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0x24,
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INST_TYPE_RD_RA,
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RD = MICROBLAZE_SEXT8(RA);
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PC += INST_SIZE)
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INSTRUCTION(sext16,
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0x24,
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INST_TYPE_RD_RA,
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RD = MICROBLAZE_SEXT16(RA);
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PC += INST_SIZE)
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INSTRUCTION(wdc,
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0x24,
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INST_TYPE_RA_RB,
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PC += INST_SIZE)
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INSTRUCTION(wic,
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0x24,
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INST_TYPE_RA_RB,
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PC += INST_SIZE)
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INSTRUCTION(mts,
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0x25,
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INST_TYPE_SA_RA,
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SA = RA;
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PC += INST_SIZE)
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INSTRUCTION(mfs,
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0x25,
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INST_TYPE_RD_SA,
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RD = SA;
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PC += INST_SIZE)
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INSTRUCTION(br,
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0x26,
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INST_TYPE_RB,
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PC += RB;
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BRANCH)
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INSTRUCTION(brd,
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0x26,
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INST_TYPE_RB,
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PC += RB;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(brld,
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0x26,
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INST_TYPE_RD_RB,
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RD = PC;
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PC += RB;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(bra,
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0x26,
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INST_TYPE_RB,
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PC = RB;
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BRANCH)
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INSTRUCTION(brad,
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0x26,
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INST_TYPE_RB,
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PC = RB;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(brald,
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0x26,
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INST_TYPE_RD_RB,
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RD = PC;
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PC = RB;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(microblaze_brk,
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0x26,
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INST_TYPE_RD_RB,
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RD = PC;
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PC = RB;
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MSR = MSR | BIP_MASK;
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BRANCH)
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INSTRUCTION(beq,
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0x27,
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INST_TYPE_RA_RB,
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if (RA == 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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})
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INSTRUCTION(beqd,
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0x27,
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INST_TYPE_RA_RB,
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if (RA == 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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}
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DELAY_SLOT)
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INSTRUCTION(bne,
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0x27,
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INST_TYPE_RA_RB,
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if (RA != 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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})
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INSTRUCTION(bned,
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0x27,
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INST_TYPE_RA_RB,
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if (RA != 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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}
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DELAY_SLOT)
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INSTRUCTION(blt,
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0x27,
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INST_TYPE_RA_RB,
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if (RA < 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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})
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INSTRUCTION(bltd,
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0x27,
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INST_TYPE_RA_RB,
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if (RA < 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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}
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DELAY_SLOT)
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INSTRUCTION(ble,
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0x27,
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INST_TYPE_RA_RB,
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if (RA <= 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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})
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INSTRUCTION(bled,
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0x27,
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INST_TYPE_RA_RB,
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if (RA <= 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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}
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DELAY_SLOT)
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INSTRUCTION(bgt,
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0x27,
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INST_TYPE_RA_RB,
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if (RA > 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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})
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INSTRUCTION(bgtd,
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0x27,
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INST_TYPE_RA_RB,
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if (RA > 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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}
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DELAY_SLOT)
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INSTRUCTION(bge,
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0x27,
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INST_TYPE_RA_RB,
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if (RA >= 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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})
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INSTRUCTION(bged,
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0x27,
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INST_TYPE_RA_RB,
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if (RA >= 0) {
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PC += RB;
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BRANCH;
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} else {
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PC += INST_SIZE;
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}
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DELAY_SLOT)
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INSTRUCTION(ori,
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0x28,
|
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INST_TYPE_RD_RA_IMM,
|
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RD = RA | IMM;
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PC += INST_SIZE)
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INSTRUCTION(andi,
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0x29,
|
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INST_TYPE_RD_RA_IMM,
|
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RD = RA & IMM;
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PC += INST_SIZE)
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INSTRUCTION(xori,
|
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0x2A,
|
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INST_TYPE_RD_RA_IMM,
|
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RD = RA ^ IMM;
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PC += INST_SIZE)
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INSTRUCTION(andni,
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0x2B,
|
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INST_TYPE_RD_RA_IMM,
|
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RD = RA & ~IMM;
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PC += INST_SIZE)
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INSTRUCTION(imm,
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0x2C,
|
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INST_TYPE_IMM,
|
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IMM_H = IMM_L;
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PC += INST_SIZE)
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INSTRUCTION(rtsd,
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0x2D,
|
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INST_TYPE_RA_IMM,
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PC = RA + IMM;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(rtid,
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0x2D,
|
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INST_TYPE_RA_IMM,
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PC = RA + IMM;
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MSR = MSR | INTR_EN_MASK;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(rtbd,
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0x2D,
|
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INST_TYPE_RA_IMM,
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PC = RA + IMM;
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MSR = MSR & ~BIP_MASK;
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BRANCH;
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DELAY_SLOT;)
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INSTRUCTION(bri,
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0x2E,
|
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INST_TYPE_IMM,
|
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PC += IMM;
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BRANCH)
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INSTRUCTION(brid,
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0x2E,
|
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INST_TYPE_IMM,
|
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PC += IMM;
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BRANCH;
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DELAY_SLOT)
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INSTRUCTION(brlid,
|
|
0x2E,
|
|
INST_TYPE_RD_IMM,
|
|
RD = PC;
|
|
PC += IMM;
|
|
BRANCH;
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(brai,
|
|
0x2E,
|
|
INST_TYPE_IMM,
|
|
PC = IMM;
|
|
BRANCH)
|
|
|
|
INSTRUCTION(braid,
|
|
0x2E,
|
|
INST_TYPE_IMM,
|
|
PC = IMM;
|
|
BRANCH;
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(bralid,
|
|
0x2E,
|
|
INST_TYPE_RD_IMM,
|
|
RD = PC;
|
|
PC = IMM;
|
|
BRANCH;
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(brki,
|
|
0x2E,
|
|
INST_TYPE_RD_IMM,
|
|
RD = PC;
|
|
PC = IMM;
|
|
MSR = MSR | BIP_MASK;
|
|
BRANCH)
|
|
|
|
INSTRUCTION(beqi,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA == 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
})
|
|
|
|
INSTRUCTION(beqid,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA == 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
}
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(bnei,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA != 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
})
|
|
|
|
INSTRUCTION(bneid,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA != 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
}
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(blti,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA < 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
})
|
|
|
|
INSTRUCTION(bltid,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA < 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
}
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(blei,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA <= 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
})
|
|
|
|
INSTRUCTION(bleid,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA <= 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
}
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(bgti,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA > 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
})
|
|
|
|
INSTRUCTION(bgtid,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA > 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
}
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(bgei,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA >= 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
})
|
|
|
|
INSTRUCTION(bgeid,
|
|
0x2F,
|
|
INST_TYPE_RA_IMM,
|
|
if (RA >= 0) {
|
|
PC += IMM;
|
|
BRANCH;
|
|
} else {
|
|
PC += INST_SIZE;
|
|
}
|
|
DELAY_SLOT)
|
|
|
|
INSTRUCTION(lbu,
|
|
0x30,
|
|
INST_TYPE_RD_RA_RB,
|
|
RD = (MEM_RD_UBYTE(RA + RB));
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(lhu,
|
|
0x31,
|
|
INST_TYPE_RD_RA_RB,
|
|
RD = (MEM_RD_UHALF((RA + RB) & ~0x1));
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(lw,
|
|
0x32,
|
|
INST_TYPE_RD_RA_RB,
|
|
RD = (MEM_RD_WORD((RA + RB) & ~0x3));
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(sb,
|
|
0x34,
|
|
INST_TYPE_RD_RA_RB,
|
|
MEM_WR_BYTE(RA + RB, RD);
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(sh,
|
|
0x35,
|
|
INST_TYPE_RD_RA_RB,
|
|
MEM_WR_HALF((RA + RB) & ~0x1, RD);
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(sw,
|
|
0x36,
|
|
INST_TYPE_RD_RA_RB,
|
|
MEM_WR_WORD((RA + RB) & ~0x3, RD);
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(lbui,
|
|
0x38,
|
|
INST_TYPE_RD_RA_IMM,
|
|
RD = (MEM_RD_UBYTE(RA + IMM));
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(lhui,
|
|
0x39,
|
|
INST_TYPE_RD_RA_IMM,
|
|
RD = (MEM_RD_UHALF((RA+IMM) & ~0x1));
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(lwi,
|
|
0x3A,
|
|
INST_TYPE_RD_RA_IMM,
|
|
RD = (MEM_RD_WORD((RA+IMM) & ~0x3));
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(sbi,
|
|
0x3C,
|
|
INST_TYPE_RD_RA_IMM,
|
|
MEM_WR_BYTE(RA + IMM, RD);
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(shi,
|
|
0x3D,
|
|
INST_TYPE_RD_RA_IMM,
|
|
MEM_WR_HALF((RA + IMM) & ~0x1, RD);
|
|
PC += INST_SIZE)
|
|
|
|
INSTRUCTION(swi,
|
|
0x3E,
|
|
INST_TYPE_RD_RA_IMM,
|
|
MEM_WR_WORD((RA + IMM) & ~0x3, RD);
|
|
PC += INST_SIZE)
|