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binutils-gdb/sim/example-synacor
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Mike Frysinger f4fdd84587 sim: fully merge sim_state_base into sim_state 
Now that all ports have migrated to the new framework, drop support
for the old sim_state_base layout.
2021-05-17 01:05:08 -04:00
..
aclocal.m4
ChangeLog sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
config.in sim: riscv: move __int128 check to configure 2021-05-16 00:04:17 -04:00
configure sim: riscv: move __int128 check to configure 2021-05-16 00:04:17 -04:00
configure.ac
interp.c sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
Makefile.in
README
README.arch-spec
sim-main.c sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
sim-main.h sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00

README 

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.