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df18fdba5d
X86 disassembler checks data and address size prefixes when displaying instruction mnemonic and operands. For the extra data and address size prefixes, their names depend only on the address mode, not the data and address size prefixes. This patch changes x86 disassembler not to check the data and address size prefix when printing extra data and address size prefixes. gas/testsuite/ * gas/i386/nops-1-core2.d: Replace data32 with data16. * gas/i386/nops-4a-i686.d: Likewise. * gas/i386/nops-5-i686.d: Likewise. * gas/i386/nops-5.d: Likewise. * gas/i386/x86-64-cbw-intel.d: Likewise. * gas/i386/x86-64-cbw.d: Likewise. * gas/i386/x86-64-io-intel.d: Likewise. * gas/i386/x86-64-io-suffix.d: Likewise. * gas/i386/x86-64-io.d: Likewise. * gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. * gas/i386/x86-64-stack-intel.d: Likewise. * gas/i386/x86-64-stack-suffix.d: Likewise. * gas/i386/x86-64-stack.d: Likewise. * gas/i386/ilp32/x86-64-cbw-intel.d: Likewise. * gas/i386/ilp32/x86-64-cbw.d: Likewise. * gas/i386/ilp32/x86-64-io-intel.d: Likewise. * gas/i386/ilp32/x86-64-io-suffix.d: Likewise. * gas/i386/ilp32/x86-64-io.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-core2.d: * gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise. * gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-5.: Likewise. * gas/i386/ilp32/x86-64-stack-intel.d: Likewise. * gas/i386/ilp32/x86-64-stack-suffix.: Likewise. * gas/i386/ilp32/x86-64-stack.d: Likewise. ld/testsuite/ * ld-x86-64/tlsbin.dd: Replace data32 with data16. * ld-x86-64/tlsdesc-nacl.pd: Likewise. * ld-x86-64/tlsgdesc.dd: Likewise. * ld-x86-64/tlsld1.dd: Likewise. * ld-x86-64/tlsld3.dd: Likewise. * ld-x86-64/tlspic.dd: Likewise. opcodes/ 2014-05-09 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (ADDR16_PREFIX): Removed. (ADDR32_PREFIX): Likewise. (DATA16_PREFIX): Likewise. (DATA32_PREFIX): Likewise. (prefix_name): Updated. (print_insn): Simplify data and address size prefixes processing.
56 lines
2.5 KiB
Plaintext
56 lines
2.5 KiB
Plaintext
#source: plt.s
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#as: --64
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#ld: -melf_x86_64_nacl
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#objdump: -drj.plt
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#target: x86_64-*-nacl*
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.*: +file format .*
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Disassembly of section .plt:
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[0-9a-f]+ <fn1@plt-0x40>:
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+[0-9a-f]+: ff 35 ([0-9a-f]{2} ){4} * pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
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+[0-9a-f]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
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+[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
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+[0-9a-f]+: 4d 01 fb add %r15,%r11
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+[0-9a-f]+: 41 ff e3 jmpq \*%r11
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+[0-9a-f]+: 66 0f 1f 84 00 00 00 nopw 0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 00 00 *
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 66 90 xchg %ax,%ax
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[0-9a-f]+ <fn1@plt>:
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+[0-9a-f]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x18>
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+[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
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+[0-9a-f]+: 4d 01 fb add %r15,%r11
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+[0-9a-f]+: 41 ff e3 jmpq \*%r11
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 68 00 00 00 00 pushq \$0x0
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+[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <fn1@plt-0x40>
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
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[0-9a-f]+ <fn2@plt>:
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+[0-9a-f]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x20>
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+[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
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+[0-9a-f]+: 4d 01 fb add %r15,%r11
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+[0-9a-f]+: 41 ff e3 jmpq \*%r11
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 68 01 00 00 00 pushq \$0x1
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+[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <fn1@plt-0x40>
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\)
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