mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
172 lines
5.4 KiB
C
172 lines
5.4 KiB
C
/* e500 expression macros, for PSIM, the PowerPC simulator.
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Copyright 2003-2024 Free Software Foundation, Inc.
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Contributed by Red Hat Inc; developed under contract from Motorola.
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Written by matthew green <mrg@redhat.com>.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* e500 register dance */
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#define EV_SET_REG4(sh, sl, h0, h1, h2, h3) do { \
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(sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \
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(sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \
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} while (0)
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#define EV_SET_REG4_ACC(sh, sl, h0, h1, h2, h3) do { \
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(sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \
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(sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \
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ACC = ((uint64_t)(sh) << 32) | (sl & 0xffffffff); \
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} while (0)
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#define EV_SET_REG2(sh, sl, dh, dl) do { \
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(sh) = (dh) & 0xffffffff; \
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(sl) = (dl) & 0xffffffff; \
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} while (0)
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#define EV_SET_REG2_ACC(sh, sl, dh, dl) do { \
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(sh) = (dh) & 0xffffffff; \
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(sl) = (dl) & 0xffffffff; \
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ACC = ((uint64_t)(sh) << 32) | ((sl) & 0xffffffff); \
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} while (0)
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#define EV_SET_REG1(sh, sl, d) do { \
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(sh) = ((uint64_t)(d) >> 32) & 0xffffffff; \
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(sl) = (d) & 0xffffffff; \
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} while (0)
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#define EV_SET_REG1_ACC(sh, sl, d) do { \
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(sh) = ((uint64_t)(d) >> 32) & 0xffffffff; \
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(sl) = (d) & 0xffffffff; \
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ACC = (d); \
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} while (0)
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#define EV_SET_REG(s, d) do { \
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(s) = (d) & 0xffffffff; \
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} while (0)
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/* get the low or high half word of a word */
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#define EV_LOHALF(x) ((uint32_t)(x) & 0xffff)
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#define EV_HIHALF(x) (((uint32_t)(x) >> 16) & 0xffff)
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/* partially visible accumulator accessors */
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#define EV_SET_ACC(rh, rl) \
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ACC = ((uint64_t)(rh) << 32) | ((rl) & 0xffffffff)
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#define EV_ACCLOW (ACC & 0xffffffff)
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#define EV_ACCHIGH ((ACC >> 32) & 0xffffffff)
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/* bit manipulation macros needed for e500 SPE */
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#define EV_BITREVERSE16(x) \
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((((x) & 0x0001) << 15) \
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| (((x) & 0x0002) << 13) \
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| (((x) & 0x0004) << 11) \
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| (((x) & 0x0008) << 9) \
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| (((x) & 0x0010) << 7) \
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| (((x) & 0x0020) << 5) \
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| (((x) & 0x0040) << 3) \
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| (((x) & 0x0080) << 1) \
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| (((x) & 0x0100) >> 1) \
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| (((x) & 0x0200) >> 3) \
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| (((x) & 0x0400) >> 5) \
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| (((x) & 0x0800) >> 7) \
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| (((x) & 0x1000) >> 9) \
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| (((x) & 0x2000) >> 11) \
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| (((x) & 0x4000) >> 13) \
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| (((x) & 0x8000) >> 15))
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/* saturation helpers */
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#define EV_MUL16_SSF(a,b) ((int64_t)((int32_t)(int16_t)(a) * (int32_t)(int16_t)(b)) << 1)
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/* this one loses the top sign bit; be careful */
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#define EV_MUL32_SSF(a,b) (((int64_t)(int32_t)(a) * (int64_t)(int32_t)(b)) << 1)
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#define EV_SAT_P_S32(x) ((((int64_t)(x)) < -0x80000000LL) || (((int64_t)(x)) > 0x7fffffffLL))
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#define EV_SAT_P_U32(x) ((((int64_t)(x)) < -0LL) || (((int64_t)(x)) > 0xffffffffLL))
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#define EV_SATURATE(flag, sat_val, val) \
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((flag) ? (sat_val) : (val))
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#define EV_SATURATE_ACC(flag, sign, negative_sat_val, positive_sat_val, val) \
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((flag) ? ((((sign) >> 63) & 1) ? (negative_sat_val) : (positive_sat_val)) : (val))
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/* SPEFSCR handling. */
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/* These bits must be clear. */
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#define EV_SPEFSCR_MASK (BIT(40) | BIT(41) | spefscr_mode | BIT(56))
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/* The Inexact and Divide by zero sticky bits are based on others. */
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#define EV_SET_SPEFSCR(bits) do { \
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int finxs = (bits) & (spefscr_fgh|spefscr_fxh|spefscr_fg|spefscr_fx); \
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int fdbzs = (bits) & (spefscr_fdbzh|spefscr_fdbz); \
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SPREG(spr_spefscr) = ((bits) & ~EV_SPEFSCR_MASK) | \
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(finxs ? spefscr_finxs : 0) | \
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(fdbzs ? spefscr_fdbzs : 0); \
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} while (0)
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#define EV_SET_SPEFSCR_BITS(s) \
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EV_SET_SPEFSCR(SPREG(spr_spefscr) | (s))
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#define EV_SET_SPEFSCR_OV(l,h) do { \
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uint32_t _sPefScR = SPREG(spr_spefscr); \
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if (l) \
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_sPefScR |= spefscr_ov | spefscr_sov; \
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else \
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_sPefScR &= ~spefscr_ov; \
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if (h) \
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_sPefScR |= spefscr_ovh | spefscr_sovh; \
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else \
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_sPefScR &= ~spefscr_ovh; \
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EV_SET_SPEFSCR(_sPefScR); \
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} while (0)
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/* SPE floating point helpers. */
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#define EV_PMAX 0x7f7fffff
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#define EV_NMAX 0xff7fffff
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#define EV_PMIN 0x00800001
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#define EV_NMIN 0x80800001
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#define EV_IS_INFDENORMNAN(x) \
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(sim_fpu_is_infinity(x) || sim_fpu_is_denorm(x) || sim_fpu_is_nan(x))
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/* These aren't used (yet?) For now, SPU is always enabled.
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Would be nice if they were generated by igen for e500. */
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#define SPU_BEGIN \
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{ \
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if (MSR & msr_e500_spu_enable) { \
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#define SPU_END \
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} else { \
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/* FIXME: raise SPU unavailable. */ \
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} \
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}
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/* These are also not yet used. */
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#define SPU_FP_BEGIN \
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{
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#define SPU_FP_END \
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{ \
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unsigned s = SPEFSCR; \
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/* Check SPEFSCR; raise exceptions if any required. */ \
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if (((spefscr_finxe || spefscr_finve) \
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&& (s & (spefscr_finvh|spefscr_finv))) \
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|| ((spefscr_finxe || spefscr_fdbze) \
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&& (s & (spefscr_fdbzh|spefscr_fdbz))) \
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|| ((spefscr_finxe || spefscr_funfe) \
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&& (s & (spefscr_funfh|spefscr_funf))) \
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|| ((spefscr_finxe || spefscr_fovfe) \
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&& (s & (spefscr_fovfh|spefscr_fovf)))) \
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/* FIXME: raise exceptions. */; \
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} \
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}
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