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8fed036bef
Some compilers warn in the frv code: sem.c:24343:41: error: incompatible function pointer types passing 'void (SIM_CPU *, UINT, UDI)' (aka 'void (struct _sim_cpu *, unsigned int, unsigned long)') to parameter of type 'void (*)(SIM_CPU *, UINT, DI)' (aka 'void (*)(struct _sim_cpu *, unsigned int, long)') [-Wincompatible-function-pointer-types] This is due to frvbf_h_acc40U_set using UDI for setting the new value, but using the common sim_queue_fn_di_write API which uses DI. The same size, but different sign. We could change frvbf_h_acc40U_set to take a DI without changing behavior in practice: the UDI is already passed via the queue function which accepts a DI, and frvbf_h_acc40U_set already casts the input to UDI before running any operations on it. However, these files are all generated, so manual changes here would be reverted. Seems like we can only change the register type for all APIs in the cpu definition. This builds cleanly, and passes sim unittests. Not sure if it's 100% the answer, but seems to be the best we have currently. Bug: https://sourceware.org/PR29752
702 lines
11 KiB
C
702 lines
11 KiB
C
/* Misc. support for CPU family frvbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2023 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#define WANT_CPU frvbf
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "cgen-ops.h"
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/* Get the value of h-reloc-ann. */
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BI
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frvbf_h_reloc_ann_get (SIM_CPU *current_cpu)
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{
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return CPU (h_reloc_ann);
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}
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/* Set a value for h-reloc-ann. */
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void
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frvbf_h_reloc_ann_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_reloc_ann) = newval;
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}
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/* Get the value of h-pc. */
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USI
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frvbf_h_pc_get (SIM_CPU *current_cpu)
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{
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return CPU (h_pc);
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}
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/* Set a value for h-pc. */
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void
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frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
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{
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CPU (h_pc) = newval;
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}
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/* Get the value of h-psr_imple. */
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UQI
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frvbf_h_psr_imple_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_imple);
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}
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/* Set a value for h-psr_imple. */
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void
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frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_psr_imple) = newval;
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}
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/* Get the value of h-psr_ver. */
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UQI
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frvbf_h_psr_ver_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_ver);
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}
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/* Set a value for h-psr_ver. */
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void
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frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_psr_ver) = newval;
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}
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/* Get the value of h-psr_ice. */
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BI
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frvbf_h_psr_ice_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_ice);
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}
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/* Set a value for h-psr_ice. */
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void
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frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_ice) = newval;
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}
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/* Get the value of h-psr_nem. */
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BI
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frvbf_h_psr_nem_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_nem);
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}
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/* Set a value for h-psr_nem. */
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void
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frvbf_h_psr_nem_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_nem) = newval;
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}
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/* Get the value of h-psr_cm. */
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BI
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frvbf_h_psr_cm_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_cm);
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}
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/* Set a value for h-psr_cm. */
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void
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frvbf_h_psr_cm_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_cm) = newval;
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}
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/* Get the value of h-psr_be. */
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BI
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frvbf_h_psr_be_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_be);
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}
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/* Set a value for h-psr_be. */
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void
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frvbf_h_psr_be_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_be) = newval;
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}
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/* Get the value of h-psr_esr. */
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BI
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frvbf_h_psr_esr_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_esr);
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}
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/* Set a value for h-psr_esr. */
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void
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frvbf_h_psr_esr_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_esr) = newval;
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}
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/* Get the value of h-psr_ef. */
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BI
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frvbf_h_psr_ef_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_ef);
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}
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/* Set a value for h-psr_ef. */
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void
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frvbf_h_psr_ef_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_ef) = newval;
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}
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/* Get the value of h-psr_em. */
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BI
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frvbf_h_psr_em_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_em);
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}
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/* Set a value for h-psr_em. */
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void
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frvbf_h_psr_em_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_em) = newval;
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}
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/* Get the value of h-psr_pil. */
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UQI
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frvbf_h_psr_pil_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_pil);
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}
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/* Set a value for h-psr_pil. */
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void
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frvbf_h_psr_pil_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_psr_pil) = newval;
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}
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/* Get the value of h-psr_ps. */
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BI
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frvbf_h_psr_ps_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_ps);
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}
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/* Set a value for h-psr_ps. */
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void
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frvbf_h_psr_ps_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_ps) = newval;
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}
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/* Get the value of h-psr_et. */
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BI
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frvbf_h_psr_et_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_et);
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}
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/* Set a value for h-psr_et. */
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void
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frvbf_h_psr_et_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_psr_et) = newval;
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}
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/* Get the value of h-psr_s. */
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BI
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frvbf_h_psr_s_get (SIM_CPU *current_cpu)
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{
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return CPU (h_psr_s);
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}
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/* Set a value for h-psr_s. */
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void
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frvbf_h_psr_s_set (SIM_CPU *current_cpu, BI newval)
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{
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SET_H_PSR_S (newval);
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}
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/* Get the value of h-tbr_tba. */
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USI
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frvbf_h_tbr_tba_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tbr_tba);
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}
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/* Set a value for h-tbr_tba. */
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void
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frvbf_h_tbr_tba_set (SIM_CPU *current_cpu, USI newval)
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{
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CPU (h_tbr_tba) = newval;
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}
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/* Get the value of h-tbr_tt. */
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UQI
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frvbf_h_tbr_tt_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tbr_tt);
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}
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/* Set a value for h-tbr_tt. */
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void
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frvbf_h_tbr_tt_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_tbr_tt) = newval;
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}
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/* Get the value of h-bpsr_bs. */
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BI
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frvbf_h_bpsr_bs_get (SIM_CPU *current_cpu)
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{
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return CPU (h_bpsr_bs);
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}
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/* Set a value for h-bpsr_bs. */
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void
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frvbf_h_bpsr_bs_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_bpsr_bs) = newval;
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}
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/* Get the value of h-bpsr_bet. */
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BI
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frvbf_h_bpsr_bet_get (SIM_CPU *current_cpu)
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{
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return CPU (h_bpsr_bet);
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}
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/* Set a value for h-bpsr_bet. */
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void
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frvbf_h_bpsr_bet_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_bpsr_bet) = newval;
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}
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/* Get the value of h-gr. */
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USI
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frvbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_GR (regno);
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}
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/* Set a value for h-gr. */
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void
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frvbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
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{
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SET_H_GR (regno, newval);
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}
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/* Get the value of h-gr_double. */
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DI
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frvbf_h_gr_double_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_GR_DOUBLE (regno);
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}
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/* Set a value for h-gr_double. */
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void
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frvbf_h_gr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval)
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{
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SET_H_GR_DOUBLE (regno, newval);
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}
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/* Get the value of h-gr_hi. */
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UHI
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frvbf_h_gr_hi_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_GR_HI (regno);
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}
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/* Set a value for h-gr_hi. */
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void
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frvbf_h_gr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_GR_HI (regno, newval);
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}
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/* Get the value of h-gr_lo. */
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UHI
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frvbf_h_gr_lo_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_GR_LO (regno);
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}
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/* Set a value for h-gr_lo. */
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void
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frvbf_h_gr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_GR_LO (regno, newval);
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}
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/* Get the value of h-fr. */
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SF
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frvbf_h_fr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR (regno);
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}
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/* Set a value for h-fr. */
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void
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frvbf_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
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{
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SET_H_FR (regno, newval);
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}
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/* Get the value of h-fr_double. */
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DF
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frvbf_h_fr_double_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_DOUBLE (regno);
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}
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/* Set a value for h-fr_double. */
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void
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frvbf_h_fr_double_set (SIM_CPU *current_cpu, UINT regno, DF newval)
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{
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SET_H_FR_DOUBLE (regno, newval);
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}
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/* Get the value of h-fr_int. */
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USI
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frvbf_h_fr_int_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_INT (regno);
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}
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/* Set a value for h-fr_int. */
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void
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frvbf_h_fr_int_set (SIM_CPU *current_cpu, UINT regno, USI newval)
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{
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SET_H_FR_INT (regno, newval);
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}
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/* Get the value of h-fr_hi. */
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UHI
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frvbf_h_fr_hi_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_HI (regno);
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}
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/* Set a value for h-fr_hi. */
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void
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frvbf_h_fr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_FR_HI (regno, newval);
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}
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/* Get the value of h-fr_lo. */
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UHI
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frvbf_h_fr_lo_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_LO (regno);
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}
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/* Set a value for h-fr_lo. */
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void
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frvbf_h_fr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_FR_LO (regno, newval);
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}
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/* Get the value of h-fr_0. */
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UHI
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frvbf_h_fr_0_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_0 (regno);
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}
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/* Set a value for h-fr_0. */
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void
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frvbf_h_fr_0_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_FR_0 (regno, newval);
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}
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/* Get the value of h-fr_1. */
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UHI
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frvbf_h_fr_1_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_1 (regno);
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}
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/* Set a value for h-fr_1. */
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void
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frvbf_h_fr_1_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_FR_1 (regno, newval);
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}
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/* Get the value of h-fr_2. */
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UHI
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frvbf_h_fr_2_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_2 (regno);
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}
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/* Set a value for h-fr_2. */
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void
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frvbf_h_fr_2_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_FR_2 (regno, newval);
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}
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/* Get the value of h-fr_3. */
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UHI
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frvbf_h_fr_3_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_FR_3 (regno);
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}
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/* Set a value for h-fr_3. */
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void
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frvbf_h_fr_3_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
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{
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SET_H_FR_3 (regno, newval);
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}
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/* Get the value of h-cpr. */
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SI
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frvbf_h_cpr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return CPU (h_cpr[regno]);
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}
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/* Set a value for h-cpr. */
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void
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frvbf_h_cpr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
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{
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CPU (h_cpr[regno]) = newval;
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}
|
|
|
|
/* Get the value of h-cpr_double. */
|
|
|
|
DI
|
|
frvbf_h_cpr_double_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return GET_H_CPR_DOUBLE (regno);
|
|
}
|
|
|
|
/* Set a value for h-cpr_double. */
|
|
|
|
void
|
|
frvbf_h_cpr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval)
|
|
{
|
|
SET_H_CPR_DOUBLE (regno, newval);
|
|
}
|
|
|
|
/* Get the value of h-spr. */
|
|
|
|
USI
|
|
frvbf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return GET_H_SPR (regno);
|
|
}
|
|
|
|
/* Set a value for h-spr. */
|
|
|
|
void
|
|
frvbf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
|
|
{
|
|
SET_H_SPR (regno, newval);
|
|
}
|
|
|
|
/* Get the value of h-accg. */
|
|
|
|
USI
|
|
frvbf_h_accg_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return GET_H_ACCG (regno);
|
|
}
|
|
|
|
/* Set a value for h-accg. */
|
|
|
|
void
|
|
frvbf_h_accg_set (SIM_CPU *current_cpu, UINT regno, USI newval)
|
|
{
|
|
SET_H_ACCG (regno, newval);
|
|
}
|
|
|
|
/* Get the value of h-acc40S. */
|
|
|
|
DI
|
|
frvbf_h_acc40S_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return GET_H_ACC40S (regno);
|
|
}
|
|
|
|
/* Set a value for h-acc40S. */
|
|
|
|
void
|
|
frvbf_h_acc40S_set (SIM_CPU *current_cpu, UINT regno, DI newval)
|
|
{
|
|
SET_H_ACC40S (regno, newval);
|
|
}
|
|
|
|
/* Get the value of h-acc40U. */
|
|
|
|
DI
|
|
frvbf_h_acc40U_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return GET_H_ACC40U (regno);
|
|
}
|
|
|
|
/* Set a value for h-acc40U. */
|
|
|
|
void
|
|
frvbf_h_acc40U_set (SIM_CPU *current_cpu, UINT regno, DI newval)
|
|
{
|
|
SET_H_ACC40U (regno, newval);
|
|
}
|
|
|
|
/* Get the value of h-iacc0. */
|
|
|
|
DI
|
|
frvbf_h_iacc0_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return GET_H_IACC0 (regno);
|
|
}
|
|
|
|
/* Set a value for h-iacc0. */
|
|
|
|
void
|
|
frvbf_h_iacc0_set (SIM_CPU *current_cpu, UINT regno, DI newval)
|
|
{
|
|
SET_H_IACC0 (regno, newval);
|
|
}
|
|
|
|
/* Get the value of h-iccr. */
|
|
|
|
UQI
|
|
frvbf_h_iccr_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return CPU (h_iccr[regno]);
|
|
}
|
|
|
|
/* Set a value for h-iccr. */
|
|
|
|
void
|
|
frvbf_h_iccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval)
|
|
{
|
|
CPU (h_iccr[regno]) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fccr. */
|
|
|
|
UQI
|
|
frvbf_h_fccr_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return CPU (h_fccr[regno]);
|
|
}
|
|
|
|
/* Set a value for h-fccr. */
|
|
|
|
void
|
|
frvbf_h_fccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval)
|
|
{
|
|
CPU (h_fccr[regno]) = newval;
|
|
}
|
|
|
|
/* Get the value of h-cccr. */
|
|
|
|
UQI
|
|
frvbf_h_cccr_get (SIM_CPU *current_cpu, UINT regno)
|
|
{
|
|
return CPU (h_cccr[regno]);
|
|
}
|
|
|
|
/* Set a value for h-cccr. */
|
|
|
|
void
|
|
frvbf_h_cccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval)
|
|
{
|
|
CPU (h_cccr[regno]) = newval;
|
|
}
|