Mike Frysinger c8c6ef3807 sim: riscv: switch to new target-newlib-syscall ... Use the new target-newlib-syscall module. This is needed to merge all the architectures into a single build, and riscv has a custom syscall table for its newlib/libgloss port.		2021-11-28 13:23:58 -05:00
..
aclocal.m4	sim: move default model to the runtime sim state	2021-06-30 02:57:45 -04:00
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
configure	sim: unify reserved instruction bits settings	2021-07-01 20:53:00 -04:00
configure.ac	sim: move default model to the runtime sim state	2021-06-30 02:57:45 -04:00
interp.c	sim: riscv: switch to new target-newlib-syscall	2021-11-28 13:23:58 -05:00
machs.c	sim: namespace sim_machs	2021-06-30 01:52:51 -04:00
machs.h
Makefile.in	sim: riscv: switch to new target-newlib-syscall	2021-11-28 13:23:58 -05:00
model_list.def
sim-main.c	sim: drop unused targ-vals.h includes	2021-10-31 04:53:22 -04:00
sim-main.h	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00