mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
0cc7872125
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.
Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.
gas/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
(cpu_arch): Add .avx512_fp16.
(cpu_noarch): Add noavx512_fp16.
(pte): Add evexmap5 and evexmap6.
(build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6.
(check_VecOperations): Handle {1to32}.
(check_VecOperands): Handle CheckRegNumb.
(check_word_reg): Handle Toqword.
(i386_error): Add invalid_dest_and_src_register_set.
(match_template): Handle invalid_dest_and_src_register_set.
* doc/c-i386.texi: Document avx512_fp16, noavx512_fp16.
opcodes/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (EXwScalarS): New.
(EXxh): Ditto.
(EXxhc): Ditto.
(EXxmmqh): Ditto.
(EXxmmqdh): Ditto.
(EXEvexXwb): Ditto.
(DistinctDest_Fixup): Ditto.
(enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode
and w_swap_mode.
(enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0,
PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56,
PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67,
PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11,
PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C,
PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F,
PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59,
PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1,
PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1,
PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E,
PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79,
PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C,
PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56,
PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7
(enum): Add EVEX_MAP5 and EVEX_MAP6.
(enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B,
EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0,
EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3,
EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2,
EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2,
(get_valid_dis386): Properly handle new instructions.
(intel_operand_size): Handle new modes.
(OP_E_memory): Ditto.
(OP_EX): Ditto.
* i386-dis-evex.h: Updated for AVX512_FP16.
* i386-dis-evex-mod.h: Updated for AVX512_FP16.
* i386-dis-evex-prefix.h: Updated for AVX512_FP16.
* i386-dis-evex-reg.h : Updated for AVX512_FP16.
* i386-dis-evex-w.h : Updated for AVX512_FP16.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS,
and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS
and CPU_ANY_AVX512BW_FLAGS.
(cpu_flags): Add CpuAVX512_FP16.
(opcode_modifiers): Add DistinctDest.
* i386-opc.h (enum): (AVX512_FP16): New.
(i386_opcode_modifier): Add reqdistinctreg.
(i386_cpu_flags): Add cpuavx512_fp16.
(EVEXMAP5): Defined as a macro.
(EVEXMAP6): Ditto.
* i386-opc.tbl: Add Intel AVX512_FP16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Ditto.
599 lines
16 KiB
C
599 lines
16 KiB
C
/* PREFIX_EVEX_0F10 */
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{
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{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F10_P_1) },
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{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F10_P_3) },
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},
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/* PREFIX_EVEX_0F11 */
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{
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{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F11_P_1) },
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{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F11_P_3) },
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},
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/* PREFIX_EVEX_0F12 */
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{
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{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_0) },
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{ VEX_W_TABLE (EVEX_W_0F12_P_1) },
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{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_2) },
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{ VEX_W_TABLE (EVEX_W_0F12_P_3) },
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},
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/* PREFIX_EVEX_0F16 */
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{
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{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_0) },
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{ VEX_W_TABLE (EVEX_W_0F16_P_1) },
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{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_2) },
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},
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/* PREFIX_EVEX_0F2A */
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{
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{ Bad_Opcode },
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{ "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ Bad_Opcode },
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{ "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* PREFIX_EVEX_0F51 */
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{
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{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F51_P_1) },
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{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F51_P_3) },
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},
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/* PREFIX_EVEX_0F58 */
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{
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{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F58_P_1) },
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{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F58_P_3) },
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},
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/* PREFIX_EVEX_0F59 */
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{
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{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F59_P_1) },
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{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F59_P_3) },
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},
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/* PREFIX_EVEX_0F5A */
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{
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{ VEX_W_TABLE (EVEX_W_0F5A_P_0) },
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{ VEX_W_TABLE (EVEX_W_0F5A_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F5A_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F5A_P_3) },
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},
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/* PREFIX_EVEX_0F5B */
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{
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{ VEX_W_TABLE (EVEX_W_0F5B_P_0) },
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{ VEX_W_TABLE (EVEX_W_0F5B_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F5B_P_2) },
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},
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/* PREFIX_EVEX_0F5C */
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{
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{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5C_P_1) },
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{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5C_P_3) },
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},
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/* PREFIX_EVEX_0F5D */
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{
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{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5D_P_1) },
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{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5D_P_3) },
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},
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/* PREFIX_EVEX_0F5E */
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{
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{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5E_P_1) },
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{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5E_P_3) },
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},
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/* PREFIX_EVEX_0F5F */
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{
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{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5F_P_1) },
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{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0F5F_P_3) },
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},
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/* PREFIX_EVEX_0F6F */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F6F_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F6F_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F6F_P_3) },
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},
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/* PREFIX_EVEX_0F70 */
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{
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{ Bad_Opcode },
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{ "vpshufhw", { XM, EXx, Ib }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F70_P_2) },
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{ "vpshuflw", { XM, EXx, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F78 */
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{
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{ VEX_W_TABLE (EVEX_W_0F78_P_0) },
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{ "vcvttss2usi", { Gdq, EXd, EXxEVexS }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F78_P_2) },
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{ "vcvttsd2usi", { Gdq, EXq, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_0F79 */
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{
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{ VEX_W_TABLE (EVEX_W_0F79_P_0) },
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{ "vcvtss2usi", { Gdq, EXd, EXxEVexR }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F79_P_2) },
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{ "vcvtsd2usi", { Gdq, EXq, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_0F7A */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7A_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F7A_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F7A_P_3) },
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},
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/* PREFIX_EVEX_0F7B */
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{
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{ Bad_Opcode },
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{ "vcvtusi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
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{ "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* PREFIX_EVEX_0F7E */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7E_P_1) },
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{ VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
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},
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/* PREFIX_EVEX_0F7F */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7F_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F7F_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F7F_P_3) },
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},
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/* PREFIX_EVEX_0FC2 */
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{
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{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0FC2_P_1) },
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{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
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{ VEX_W_TABLE (EVEX_W_0FC2_P_3) },
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},
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/* PREFIX_EVEX_0FE6 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0FE6_P_1) },
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{ VEX_W_TABLE (EVEX_W_0FE6_P_2) },
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{ VEX_W_TABLE (EVEX_W_0FE6_P_3) },
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},
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/* PREFIX_EVEX_0F3810 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3810_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3810_P_2) },
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},
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/* PREFIX_EVEX_0F3811 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3811_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3811_P_2) },
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},
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/* PREFIX_EVEX_0F3812 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3812_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3812_P_2) },
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},
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/* PREFIX_EVEX_0F3813 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3813_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3813_P_2) },
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},
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/* PREFIX_EVEX_0F3814 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3814_P_1) },
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{ "vprorv%DQ", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3815 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3815_P_1) },
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{ "vprolv%DQ", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3820 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3820_P_1) },
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{ "vpmovsxbw", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3821 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3821_P_1) },
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{ "vpmovsxbd", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3822 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3822_P_1) },
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{ "vpmovsxbq", { XM, EXxmmdw }, 0 },
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},
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/* PREFIX_EVEX_0F3823 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3823_P_1) },
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{ "vpmovsxwd", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3824 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3824_P_1) },
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{ "vpmovsxwq", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3825 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3825_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3825_P_2) },
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},
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/* PREFIX_EVEX_0F3826 */
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{
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{ Bad_Opcode },
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{ "vptestnm%BW", { MaskG, Vex, EXx }, 0 },
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{ "vptestm%BW", { MaskG, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3827 */
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{
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{ Bad_Opcode },
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{ "vptestnm%DQ", { MaskG, Vex, EXx }, 0 },
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{ "vptestm%DQ", { MaskG, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3828 */
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{
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{ Bad_Opcode },
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{ MOD_TABLE (MOD_EVEX_0F3828_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3828_P_2) },
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},
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/* PREFIX_EVEX_0F3829 */
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{
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{ Bad_Opcode },
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{ "vpmov%BW2m", { MaskG, EXx }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F3829_P_2) },
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},
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/* PREFIX_EVEX_0F382A */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F382A_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F382A_P_2) },
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},
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/* PREFIX_EVEX_0F3830 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3830_P_1) },
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{ "vpmovzxbw", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3831 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3831_P_1) },
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{ "vpmovzxbd", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3832 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3832_P_1) },
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{ "vpmovzxbq", { XM, EXxmmdw }, 0 },
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},
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/* PREFIX_EVEX_0F3833 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3833_P_1) },
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{ "vpmovzxwd", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3834 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3834_P_1) },
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{ "vpmovzxwq", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3835 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3835_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3835_P_2) },
|
|
},
|
|
/* PREFIX_EVEX_0F3838 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ MOD_TABLE (MOD_EVEX_0F3838_P_1) },
|
|
{ "vpminsb", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3839 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpmov%DQ2m", { MaskG, EXx }, 0 },
|
|
{ "vpmins%DQ", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F383A */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_0F383A_P_1) },
|
|
{ "vpminuw", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3852 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_0F3852_P_1) },
|
|
{ "vpdpwssd", { XM, Vex, EXx }, 0 },
|
|
{ "vp4dpwssd", { XM, Vex, EXxmm }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3853 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vpdpwssds", { XM, Vex, EXx }, 0 },
|
|
{ "vp4dpwssds", { XM, Vex, EXxmm }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3868 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vp2intersect%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3872 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_0F3872_P_1) },
|
|
{ VEX_W_TABLE (EVEX_W_0F3872_P_2) },
|
|
{ VEX_W_TABLE (EVEX_W_0F3872_P_3) },
|
|
},
|
|
/* PREFIX_EVEX_0F389A */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vfmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
|
|
{ "v4fmaddps", { XM, Vex, Mxmm }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F389B */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vfmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
|
|
{ "v4fmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F38AA */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vfmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
|
|
{ "v4fnmaddps", { XM, Vex, Mxmm }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F38AB */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
|
|
{ "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A08_W_0 */
|
|
{
|
|
{ "vrndscaleph", { XM, EXxh, EXxEVexS, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vrndscaleps", { XM, EXx, EXxEVexS, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A0A_W_0 */
|
|
{
|
|
{ "vrndscalesh", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vrndscaless", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A26 */
|
|
{
|
|
{ "vgetmantp%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vgetmantp%XW", { XM, EXx, EXxEVexS, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A27 */
|
|
{
|
|
{ "vgetmants%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vgetmants%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A56 */
|
|
{
|
|
{ "vreducep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vreducep%XW", { XM, EXx, EXxEVexS, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A57 */
|
|
{
|
|
{ "vreduces%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vreduces%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A66 */
|
|
{
|
|
{ "vfpclassp%XH%XZ", { MaskG, EXxh, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3A67 */
|
|
{
|
|
{ "vfpclasss%XH", { MaskG, EXw, Ib }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfpclasss%XW", { MaskG, EXdq, Ib }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_0F3AC2 */
|
|
{
|
|
{ "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 },
|
|
{ "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_10 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vmovs%XH", { XMScalar, VexScalarR, EXw }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_11 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vmovs%XH", { EXwS, VexScalarR, XMScalar }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_1D */
|
|
{
|
|
{ "vcvtss2s%XH", { XMM, VexScalar, EXd, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vcvtps2p%XHx%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_2A */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vcvtsi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_2C */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vcvttsh2si", { Gdq, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_2D */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vcvtsh2si", { Gdq, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_2E */
|
|
{
|
|
{ "vucomis%XH", { XMScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_2F */
|
|
{
|
|
{ "vcomis%XH", { XMScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_51 */
|
|
{
|
|
{ "vsqrtp%XH", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vsqrts%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_58 */
|
|
{
|
|
{ "vaddp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
|
|
{ "vadds%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_59 */
|
|
{
|
|
{ "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
|
|
{ "vmuls%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5A_W_0 */
|
|
{
|
|
{ "vcvtph2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
|
|
{ "vcvtsh2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5A_W_1 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vcvtpd2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
|
|
{ "vcvtsd2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5B_W_0 */
|
|
{
|
|
{ "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
|
|
{ "vcvttph2dq", { XM, EXxmmqh, EXxEVexS }, 0 },
|
|
{ "vcvtph2dq", { XM, EXxmmqh, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5B_W_1 */
|
|
{
|
|
{ "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5C */
|
|
{
|
|
{ "vsubp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
|
|
{ "vsubs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5D */
|
|
{
|
|
{ "vminp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
|
|
{ "vmins%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5E */
|
|
{
|
|
{ "vdivp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
|
|
{ "vdivs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5F */
|
|
{
|
|
{ "vmaxp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
|
|
{ "vmaxs%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_78 */
|
|
{
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_78_P_0) },
|
|
{ "vcvttsh2usi", { Gdq, EXw, EXxEVexS }, 0 },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_78_P_2) },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_79 */
|
|
{
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_79_P_0) },
|
|
{ "vcvtsh2usi", { Gdq, EXw, EXxEVexR }, 0 },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_79_P_2) },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7A */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_7A_P_2) },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_7A_P_3) },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7B */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vcvtusi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_7B_P_2) },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7C */
|
|
{
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_7C_P_0) },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_7C_P_2) },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7D_W_0 */
|
|
{
|
|
{ "vcvtph2uw", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vcvtw2ph", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vcvtph2w", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vcvtuw2ph", { XM, EXxh, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_13 */
|
|
{
|
|
{ VEX_W_TABLE (EVEX_W_MAP6_13_P_0) },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_MAP6_13_P_2) },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_56 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmaddcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmaddcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_57 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_D6 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmulcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmulcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_D7 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
},
|