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6a2619f953
With this change all gas and most ld tests pass when configured for arm-linux. It doesn't look like these configurations have been tested in a long time but this attempts to stem the bit-rot slightly. gas/testsuite/ChangeLog: 2014-07-10 Will Newton <will.newton@linaro.org> * gas/arm/bl-local-2.d: Only enable the test on EABI and NaCl configurations. * gas/arm/bl-local-v4t.d: Likewise. * gas/arm/blx-local.d: Likewise. * gas/arm/branch-reloc.d: Likewise. ld/testsuite/ChangeLog: 2014-07-10 Will Newton <will.newton@linaro.org> * ld-arm/arm-elf.exp (armelftests_nonacl): Move Cortex-A8 fix tests, IFUNC tests and other EABI requiring tests to... (armeabitests_nonacl): ...here. * ld-arm/arm-app-abs32.d: Loosen regex for architecture type to allow test to pass on configurations without an attributes section. * ld-arm/arm-app.d: Likewise. * ld-arm/arm-lib-plt32.d: Likewise. * ld-arm/arm-lib.d: Likewise. * ld-arm/arm-static-app.d: Likewise. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/cortex-a8-far.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise. * ld-arm/tls-app.d: Likewise. * ld-arm/tls-descrelax-be32.d: Likewise. * ld-arm/tls-descrelax.d: Likewise. * ld-arm/tls-descseq.d: Likewise. * ld-arm/tls-gdesc-got.d: Likewise. * ld-arm/tls-gdesc.d: Likewise. * ld-arm/tls-gdierelax.d: Likewise. * ld-arm/tls-gdierelax2.d: Likewise. * ld-arm/tls-gdlerelax.d: Likewise. * ld-arm/tls-lib-loc.d: Likewise. * ld-arm/tls-lib.d: Likewise. * ld-arm/tls-thumb1.d: Likewise.
75 lines
2.2 KiB
Makefile
75 lines
2.2 KiB
Makefile
.*: file format elf32-.*arm
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architecture: arm.*, flags 0x00000150:
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HAS_SYMS, DYNAMIC, D_PAGED
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start address 0x.*
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Disassembly of section .plt:
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00008164 <.plt>:
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8164: e52de004 push {lr} ; .*
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8168: e59fe004 ldr lr, \[pc, #4\] ; .*
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816c: e08fe00e add lr, pc, lr
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8170: e5bef008 ldr pc, \[lr, #8\]!
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8174: 000080f0 .word 0x000080f0
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8178: e08e0000 add r0, lr, r0
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817c: e5901004 ldr r1, \[r0, #4\]
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8180: e12fff11 bx r1
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8184: e52d2004 push {r2} ; .*
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8188: e59f200c ldr r2, \[pc, #12\] ; .*
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818c: e59f100c ldr r1, \[pc, #12\] ; .*
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8190: e79f2002 ldr r2, \[pc, r2\]
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8194: e081100f add r1, r1, pc
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8198: e12fff12 bx r2
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819c: 000080e8 .word 0x000080e8
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81a0: 000080c8 .word 0x000080c8
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Disassembly of section .text:
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000081a8 <text>:
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81a8: e59f0004 ldr r0, \[pc, #4\] ; .*
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81ac: ebfffff1 bl 8178 .*
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81b0: e1a00000 nop ; .*
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81b4: 000080c0 .word 0x000080c0
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81b8: 4801 ldr r0, \[pc, #4\] ; .*
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81ba: f000 f805 bl 81c8 .*
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81be: 46c0 nop ; .*
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81c0: 000080b1 .word 0x000080b1
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81c4: 00000000 .word 0x00000000
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000081c8 <__unnamed_veneer>:
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81c8: 4778 bx pc
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81ca: 46c0 nop ; .*
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81cc: e59f1000 ldr r1, \[pc\] ; .*
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81d0: e081f00f add pc, r1, pc
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81d4: ffffffa0 .word 0xffffffa0
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Disassembly of section .foo:
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04001000 <foo>:
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4001000: e59f0004 ldr r0, \[pc, #4\] ; .*
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4001004: eb000009 bl 4001030 .*
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4001008: e1a00000 nop ; .*
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400100c: fc00f268 .word 0xfc00f268
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4001010: e59f0004 ldr r0, \[pc, #4\] ; .*
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4001014: eb000005 bl 4001030 .*
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4001018: e1a00000 nop ; .*
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400101c: fc00f260 .word 0xfc00f260
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4001020: 4801 ldr r0, \[pc, #4\] ; .*
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4001022: f000 f80b bl 400103c .*
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4001026: 46c0 nop ; .*
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4001028: fc00f249 .word 0xfc00f249
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400102c: 00000000 .word 0x00000000
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04001030 <__unnamed_veneer>:
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4001030: e59f1000 ldr r1, \[pc\] ; .*
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4001034: e08ff001 add pc, pc, r1
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4001038: fc00713c .word 0xfc00713c
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0400103c <__unnamed_veneer>:
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400103c: 4778 bx pc
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400103e: 46c0 nop ; .*
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4001040: e59f1000 ldr r1, \[pc\] ; .*
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4001044: e081f00f add pc, r1, pc
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4001048: fc00712c .word 0xfc00712c
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400104c: 00000000 .word 0x00000000
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