Alan Modra 2420fff633 PowerPC64 --plt-align ... This changes the PowerPC64 --plt-align option to perform the usual alignment of code as suggested by its name, as well as the previous behaviour of padding so as to reduce boundary crossing. The old behaviour is had by using a negative parameter. The default is also changed to align plt stub code by default to 32 byte boundaries, the point being to get better bctr branch prediction on power8 and power9 hardware. bfd/ * elf64-ppp.c (plt_stub_pad): Handle positive and negative plt_stub_align. ld/ * ld.texinfo (--plt-align): Describe new behaviour of option. * emultempl/ppc64elf.em (params): Default plt_stub_align to 5. * testsuite/ld-powerpc/powerpc.exp: Pass --no-plt-align for selected tests. * testsuite/ld-powerpc/relbrlt.d: Pass --no-plt-align. * testsuite/ld-powerpc/elfv2so.d: Adjust expected output.		2017-09-10 01:55:16 +09:30
..
addpcis.d	PowerPC addpcis fix	2017-02-28 11:59:47 +10:30
addpcis.s
aix52.exp
aix-abs-branch-1.dd
aix-abs-branch-1.ex
aix-abs-branch-1.im
aix-abs-branch-1.nd
aix-abs-branch-1.s
aix-abs-reloc-1.ex
aix-abs-reloc-1.im
aix-abs-reloc-1.nd
aix-abs-reloc-1.od
aix-abs-reloc-1.s
aix-core-sec-1.ex
aix-core-sec-1.hd
aix-core-sec-1.s
aix-core-sec-2.ex
aix-core-sec-2.hd
aix-core-sec-2.s
aix-core-sec-3.ex
aix-core-sec-3.hd
aix-core-sec-3.s
aix-export-1-all.dd
aix-export-1-full.dd
aix-export-1a.s
aix-export-1b.s
aix-export-2.nd
aix-export-2.s
aix-gc-1-32.dd
aix-gc-1-64.dd
aix-gc-1.ex
aix-gc-1.nd
aix-gc-1.s
aix-glink-1-32.d
aix-glink-1-32.dd
aix-glink-1-64.d
aix-glink-1-64.dd
aix-glink-1.ex
aix-glink-1.s
aix-glink-2-32.dd
aix-glink-2-64.dd
aix-glink-2a.ex
aix-glink-2a.s
aix-glink-2b.s
aix-glink-2c.ex
aix-glink-2c.s
aix-glink-2d.s
aix-glink-3-32.d
aix-glink-3-64.d
aix-glink-3.dd
aix-glink-3.s
aix-glink-3a.s
aix-glink-3b.s
aix-lineno-1.s
aix-lineno-1.txt
aix-lineno-1a.dd
aix-lineno-1a.nd
aix-lineno-1b.dd
aix-lineno-1b.nd
aix-no-dup-syms-1-dso.dnd
aix-no-dup-syms-1-dso.drd
aix-no-dup-syms-1-dso.nd
aix-no-dup-syms-1-dso.rd
aix-no-dup-syms-1-rel.nd
aix-no-dup-syms-1-rel.rd
aix-no-dup-syms-1.ex
aix-no-dup-syms-1.im
aix-no-dup-syms-1a.s
aix-no-dup-syms-1b.s
aix-ref-1-32.od
aix-ref-1-64.od
aix-ref-1.s
aix-rel-1.od
aix-rel-1.s
aix-toc-1-32.dd
aix-toc-1-64.dd
aix-toc-1.ex
aix-toc-1a.s
aix-toc-1b.s
aix-weak-1-dso.dnd
aix-weak-1-dso.hd
aix-weak-1-dso.nd
aix-weak-1-gcdso.dnd
aix-weak-1-gcdso.hd
aix-weak-1-gcdso.nd
aix-weak-1-rel.hd
aix-weak-1-rel.nd
aix-weak-1.ex
aix-weak-1a.s
aix-weak-1b.s
aix-weak-2a.ex
aix-weak-2a.nd
aix-weak-2a.s
aix-weak-2b.nd
aix-weak-2b.s
aix-weak-2c.ex
aix-weak-2c.nd
aix-weak-2c.od
aix-weak-2c.s
aix-weak-3-32.d
aix-weak-3-32.dd
aix-weak-3-64.d
aix-weak-3-64.dd
aix-weak-3a.ex
aix-weak-3a.s
aix-weak-3b.ex
aix-weak-3b.s
ambiguousv1.d	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
ambiguousv1b.d	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
ambiguousv2.d	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
ambiguousv2b.d	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
apuinfo1.s
apuinfo2.s
apuinfo-nul1.s
apuinfo-nul.rd
apuinfo-nul.s
apuinfo-vle2.s
apuinfo-vle.rd
apuinfo-vle.s
apuinfo.rd
attr-gnu-4-0.s
attr-gnu-4-1.s
attr-gnu-4-2.s
attr-gnu-4-3.s
attr-gnu-4-00.d
attr-gnu-4-01.d
attr-gnu-4-02.d
attr-gnu-4-03.d
attr-gnu-4-10.d
attr-gnu-4-11.d
attr-gnu-4-12.d
attr-gnu-4-13.d
attr-gnu-4-20.d
attr-gnu-4-21.d
attr-gnu-4-22.d
attr-gnu-4-23.d
attr-gnu-4-31.d
attr-gnu-4-32.d
attr-gnu-4-33.d
attr-gnu-8-1.s
attr-gnu-8-2.s
attr-gnu-8-3.s
attr-gnu-8-11.d
attr-gnu-8-23.d
attr-gnu-8-31.d
attr-gnu-12-1.s
attr-gnu-12-2.s
attr-gnu-12-11.d
attr-gnu-12-21.d
defsym.d
defsym.s
dotsym1.d
dotsym2.d
dotsym3.d
dotsym4.d
dotsymref.s
elfv2-2a.s
elfv2-2b.s
elfv2-2exe.d
elfv2-2so.d
elfv2.s
elfv2exe.d
elfv2so.d	PowerPC64 --plt-align	2017-09-10 01:55:16 +09:30
export-class.exp
funref2.s
funref.s
funv1.s
funv2.s
nodotsym.s
oldtlslib.s
plt1.d
plt1.s
powerpc-32-export-class.rd
powerpc-32-export-class.xd
powerpc-64-export-class.rd
powerpc-64-export-class.xd
powerpc.exp	PowerPC64 --plt-align	2017-09-10 01:55:16 +09:30
ppc476-shared2.d	Make ppc476 testcases more robust	2017-07-07 23:53:18 +09:30
ppc476-shared.d	Make ppc476 testcases more robust	2017-07-07 23:53:18 +09:30
ppc476-shared.lnk	Make ppc476 testcases more robust	2017-07-07 23:53:18 +09:30
ppc476-shared.s
relax.d
relax.s
relaxr.d
relbrlt.d	PowerPC64 --plt-align	2017-09-10 01:55:16 +09:30
relbrlt.s
reloc.d
reloc.s
relocsort.d
relocsort.s
sdabase2.d
sdabase2.t
sdabase.d
sdabase.s
sdabase.t
sdadyn.d
sdadyn.s
sdalib.s
startv1.s
startv2.s
symtocbase-1.s
symtocbase-2.s
symtocbase.d
tls32.d
tls32.g
tls32.s	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tls32.t
tls.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tls.g
tls.s	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tls.t
tlsdll_32.s
tlsdll.s
tlsdll.ver
tlsexe32.d
tlsexe32.g
tlsexe32.r
tlsexe32.t
tlsexe.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tlsexe.g
tlsexe.r
tlsexe.t
tlsexetoc.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tlsexetoc.g
tlsexetoc.r
tlsexetoc.t
tlsld32.d
tlsld32.s
tlsld.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tlsld.s
tlslib32.s
tlslib.s
tlsmark32.d
tlsmark32.s
tlsmark.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tlsmark.s
tlsopt1_32.d	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt1_32.s	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt1.d
tlsopt1.s
tlsopt2_32.d	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt2_32.s	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt2.d
tlsopt2.s
tlsopt3_32.d	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt3_32.s	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt3.d
tlsopt3.s
tlsopt4_32.d
tlsopt4_32.s	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt4.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tlsopt4.s
tlsopt5_32.d	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
tlsopt5_32.s	ppc32 tlsopt tests	2017-07-14 22:51:01 +09:30
tlsopt5.d	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
tlsopt5.s	__tls_get_addr_opt stub eh_frame info	2017-07-25 15:14:39 +09:30
tlsopt5.wf	Support different ld --hash-style in the ld testsuite	2017-08-07 22:10:51 +09:30
tlsso32.d
tlsso32.g
tlsso32.r
tlsso32.t
tlsso.d
tlsso.g
tlsso.r
tlsso.t
tlstoc.d	PowerPC TPREL16_HA/LO reloc optimization	2017-08-30 20:43:31 +09:30
tlstoc.g
tlstoc.s
tlstoc.t
tlstocso.d
tlstocso.g
tlstocso.r
tlstocso.t
tocnovar.d
tocnovar.s
tocopt2.d
tocopt2.out
tocopt2.s
tocopt3.d
tocopt3.s
tocopt4.d
tocopt4a.s
tocopt4b.s
tocopt5.d
tocopt5.s
tocopt6-inc.s
tocopt6.d
tocopt6a.s
tocopt6b.s
tocopt6c.s
tocopt7.d
tocopt7.out
tocopt7.s
tocopt8.d
tocopt8.s
tocopt.d
tocopt.out
tocopt.s
tocsave1.s	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocsave1a.d	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocsave1s.d	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocsave2.s	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocsave2a.d	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocsave2s.d	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocsavelib.s	PowerPC64 tocsave testcases	2017-06-21 22:45:15 +09:30
tocvar.d
tocvar.s
vle-multiseg-1.d
vle-multiseg-1.ld
vle-multiseg-2.d
vle-multiseg-2.ld
vle-multiseg-3.d
vle-multiseg-3.ld
vle-multiseg-4.d
vle-multiseg-4.ld
vle-multiseg-5.d
vle-multiseg-5.ld
vle-multiseg-6.d
vle-multiseg-6.ld
vle-multiseg-6a.s
vle-multiseg-6b.s
vle-multiseg-6c.s
vle-multiseg-6d.s
vle-multiseg.s
vle-reloc-1.d
vle-reloc-1.s
vle-reloc-2.d
vle-reloc-2.s
vle-reloc-3.d
vle-reloc-3.s
vle-reloc-def-1.s
vle-reloc-def-2.s
vle-reloc-def-3.s
vle.ld
vxworks1-lib.dd
vxworks1-lib.nd
vxworks1-lib.rd
vxworks1-lib.s
vxworks1-lib.sd
vxworks1-lib.td
vxworks1-static.d
vxworks1.dd
vxworks1.ld
vxworks1.rd
vxworks1.s
vxworks2-static.sd
vxworks2.s
vxworks2.sd
vxworks-relax-2.rd
vxworks-relax-2.s
vxworks-relax.rd
vxworks-relax.s