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78e9aa70fe
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
/* Copyright 2009-2015 Free Software Foundation, Inc.
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This file is part of the Xilinx MicroBlaze simulator.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#ifndef MICROBLAZE_SIM_MAIN
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#define MICROBLAZE_SIM_MAIN
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#include "microblaze.h"
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#include "sim-basics.h"
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typedef address_word sim_cia;
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#define CIA_GET(cpu) (cpu)->microblaze_cpu.spregs[0]
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#define CIA_SET(cpu,val) (cpu)->microblaze_cpu.spregs[0] = (val)
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typedef struct _sim_cpu SIM_CPU;
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#include "sim-base.h"
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/* The machine state.
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This state is maintained in host byte order. The
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fetch/store register functions must translate between host
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byte order and the target processor byte order.
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Keeping this data in target byte order simplifies the register
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read/write functions. Keeping this data in native order improves
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the performance of the simulator. Simulation speed is deemed more
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important. */
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/* The ordering of the microblaze_regset structure is matched in the
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gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */
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struct microblaze_regset
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{
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word regs[32]; /* primary registers */
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word spregs[2]; /* pc + msr */
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int cycles;
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int insts;
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int exception;
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unsigned long msize;
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unsigned char *memory;
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ubyte imm_enable;
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half imm_high;
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};
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struct _sim_cpu {
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struct microblaze_regset microblaze_cpu;
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sim_cpu_base base;
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};
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struct sim_state {
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sim_cpu *cpu[MAX_NR_PROCESSORS];
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sim_state_base base;
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};
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#endif /* MICROBLAZE_SIM_MAIN */
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