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106 lines
6.7 KiB
C
106 lines
6.7 KiB
C
/* Decode header for or1k32bf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2021 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef OR1K32BF_DECODE_H
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#define OR1K32BF_DECODE_H
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extern const IDESC *or1k32bf_decode (SIM_CPU *, IADDR,
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CGEN_INSN_WORD, CGEN_INSN_WORD,
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ARGBUF *);
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extern void or1k32bf_init_idesc_table (SIM_CPU *);
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extern void or1k32bf_sem_init_idesc_table (SIM_CPU *);
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extern void or1k32bf_semf_init_idesc_table (SIM_CPU *);
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/* Enum declaration for instructions in cpu family or1k32bf. */
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typedef enum or1k32bf_insn_type {
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OR1K32BF_INSN_X_INVALID, OR1K32BF_INSN_X_AFTER, OR1K32BF_INSN_X_BEFORE, OR1K32BF_INSN_X_CTI_CHAIN
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, OR1K32BF_INSN_X_CHAIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_INSN_L_J, OR1K32BF_INSN_L_ADRP
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, OR1K32BF_INSN_L_JAL, OR1K32BF_INSN_L_JR, OR1K32BF_INSN_L_JALR, OR1K32BF_INSN_L_BNF
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, OR1K32BF_INSN_L_BF, OR1K32BF_INSN_L_TRAP, OR1K32BF_INSN_L_SYS, OR1K32BF_INSN_L_MSYNC
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, OR1K32BF_INSN_L_PSYNC, OR1K32BF_INSN_L_CSYNC, OR1K32BF_INSN_L_RFE, OR1K32BF_INSN_L_NOP_IMM
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, OR1K32BF_INSN_L_MOVHI, OR1K32BF_INSN_L_MACRC, OR1K32BF_INSN_L_MFSPR, OR1K32BF_INSN_L_MTSPR
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, OR1K32BF_INSN_L_LWZ, OR1K32BF_INSN_L_LWS, OR1K32BF_INSN_L_LWA, OR1K32BF_INSN_L_LBZ
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, OR1K32BF_INSN_L_LBS, OR1K32BF_INSN_L_LHZ, OR1K32BF_INSN_L_LHS, OR1K32BF_INSN_L_SW
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, OR1K32BF_INSN_L_SB, OR1K32BF_INSN_L_SH, OR1K32BF_INSN_L_SWA, OR1K32BF_INSN_L_SLL
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, OR1K32BF_INSN_L_SLLI, OR1K32BF_INSN_L_SRL, OR1K32BF_INSN_L_SRLI, OR1K32BF_INSN_L_SRA
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, OR1K32BF_INSN_L_SRAI, OR1K32BF_INSN_L_ROR, OR1K32BF_INSN_L_RORI, OR1K32BF_INSN_L_AND
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, OR1K32BF_INSN_L_OR, OR1K32BF_INSN_L_XOR, OR1K32BF_INSN_L_ADD, OR1K32BF_INSN_L_SUB
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, OR1K32BF_INSN_L_ADDC, OR1K32BF_INSN_L_MUL, OR1K32BF_INSN_L_MULD, OR1K32BF_INSN_L_MULU
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, OR1K32BF_INSN_L_MULDU, OR1K32BF_INSN_L_DIV, OR1K32BF_INSN_L_DIVU, OR1K32BF_INSN_L_FF1
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, OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI, OR1K32BF_INSN_L_XORI
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, OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI, OR1K32BF_INSN_L_EXTHS
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, OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ, OR1K32BF_INSN_L_EXTWS
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, OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTSI
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, OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES, OR1K32BF_INSN_L_SFGESI
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, OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTSI
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, OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFLESI
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, OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI
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, OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC, OR1K32BF_INSN_L_MACI
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, OR1K32BF_INSN_L_MACU, OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MSBU, OR1K32BF_INSN_L_CUST1
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, OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5
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, OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S
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, OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_MUL_S
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, OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_REM_S
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, OR1K32BF_INSN_LF_REM_D32, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_FTOI_S
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, OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_SFEQ_S, OR1K32BF_INSN_LF_SFEQ_D32, OR1K32BF_INSN_LF_SFNE_S
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, OR1K32BF_INSN_LF_SFNE_D32, OR1K32BF_INSN_LF_SFGE_S, OR1K32BF_INSN_LF_SFGE_D32, OR1K32BF_INSN_LF_SFGT_S
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, OR1K32BF_INSN_LF_SFGT_D32, OR1K32BF_INSN_LF_SFLT_S, OR1K32BF_INSN_LF_SFLT_D32, OR1K32BF_INSN_LF_SFLE_S
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, OR1K32BF_INSN_LF_SFLE_D32, OR1K32BF_INSN_LF_SFUEQ_S, OR1K32BF_INSN_LF_SFUEQ_D32, OR1K32BF_INSN_LF_SFUNE_S
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, OR1K32BF_INSN_LF_SFUNE_D32, OR1K32BF_INSN_LF_SFUGT_S, OR1K32BF_INSN_LF_SFUGT_D32, OR1K32BF_INSN_LF_SFUGE_S
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, OR1K32BF_INSN_LF_SFUGE_D32, OR1K32BF_INSN_LF_SFULT_S, OR1K32BF_INSN_LF_SFULT_D32, OR1K32BF_INSN_LF_SFULE_S
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, OR1K32BF_INSN_LF_SFULE_D32, OR1K32BF_INSN_LF_SFUN_S, OR1K32BF_INSN_LF_SFUN_D32, OR1K32BF_INSN_LF_MADD_S
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, OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_INSN__MAX
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} OR1K32BF_INSN_TYPE;
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/* Enum declaration for semantic formats in cpu family or1k32bf. */
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typedef enum or1k32bf_sfmt_type {
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OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_ADRP, OR1K32BF_SFMT_L_JAL
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, OR1K32BF_SFMT_L_JR, OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP
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, OR1K32BF_SFMT_L_MSYNC, OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC
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, OR1K32BF_SFMT_L_MFSPR, OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS
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, OR1K32BF_SFMT_L_LWA, OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ
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, OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH
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, OR1K32BF_SFMT_L_SWA, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND
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, OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_MUL, OR1K32BF_SFMT_L_MULD
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, OR1K32BF_SFMT_L_MULU, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_DIVU, OR1K32BF_SFMT_L_FF1
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, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_MULI
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, OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
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, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_MACU, OR1K32BF_SFMT_LF_ADD_S
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, OR1K32BF_SFMT_LF_ADD_D32, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_D32, OR1K32BF_SFMT_LF_FTOI_S
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, OR1K32BF_SFMT_LF_FTOI_D32, OR1K32BF_SFMT_LF_SFEQ_S, OR1K32BF_SFMT_LF_SFEQ_D32, OR1K32BF_SFMT_LF_MADD_S
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, OR1K32BF_SFMT_LF_MADD_D32
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} OR1K32BF_SFMT_TYPE;
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/* Function unit handlers (user written). */
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extern int or1k32bf_model_or1200_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
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extern int or1k32bf_model_or1200nd_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
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/* Profiling before/after handlers (user written) */
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extern void or1k32bf_model_insn_before (SIM_CPU *, int /*first_p*/);
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extern void or1k32bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
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#endif /* OR1K32BF_DECODE_H */
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