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https://sourceware.org/git/binutils-gdb.git
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f36ce378b4
Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct
linker script rather than set elf[32|64]lriscv directly.
gas/
* testsuite/gas/riscv/li32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/gas/riscv/li64.d: Likewise.
* testsuite/gas/riscv/lla32.d: Likewise.
* testsuite/gas/riscv/lla64.d: Likewise.
* testsuite/gas/riscv/march-ok-g2.d: Likewise.
* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
* testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added
riscv_choose_[ilp32|lp64]_emul to choose the correct linker script.
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
* testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
* testsuite/ld-riscv-elf/c-lui.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
* testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/ld-riscv-elf/weakref64.d: Likewise.
21 lines
712 B
Makefile
21 lines
712 B
Makefile
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.*: file format elf32-(little|big)riscv
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Disassembly of section \.text:
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90000000 <_start>:
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90000000: 00000793 li a5,0
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90000004: 02078663 beqz a5,90000030 <_start\+0x30>
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90000008: 00000793 li a5,0
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9000000c: 02078263 beqz a5,90000030 <_start\+0x30>
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90000010: ff010113 addi sp,sp,-16
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90000014: 00112623 sw ra,12\(sp\)
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90000018: 00000097 auipc ra,0x0
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9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000>
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90000020: 00c12083 lw ra,12\(sp\)
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90000024: 01010113 addi sp,sp,16
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90000028: 00000317 auipc t1,0x0
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9000002c: 00000067 jr zero # 0 <_start\-0x90000000>
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90000030: 00008067 ret
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