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https://sourceware.org/git/binutils-gdb.git
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bab91cce20
bfd/ PR ld/17415 * elfnn-aarch64.c (elfNN_aarch64_howto_table): Mark R_AARCH64_TLSLE_ADD_TPREL_HI12 as complain_overflow_unsigned. * elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Correct the bit mask. ld/testsuite/ PR ld/17415 * ld-aarch64/pr17415.s: Source file for new test. * ld-aarch64/pr17415.d: Expect file for new test. * ld-aarch64/aarch64-elf.exp: Run the new test.
44 lines
649 B
ArmAsm
44 lines
649 B
ArmAsm
.cpu generic
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.global ff
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.section .tbss,"awT",%nobits
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.align 3
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.type ff, %object
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.size ff, 67108864
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ff:
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.zero 67108864
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.global i
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.align 2
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.type i, %object
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.size i, 4
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i:
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.zero 4
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.text
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.align 2
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.global main
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.type main, %function
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main:
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sub sp, sp, #16
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str wzr, [sp,12]
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b .L2
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.L3:
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mrs x0, tpidr_el0
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add x1, x0, #:tprel_hi12:ff
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add x1, x1, #:tprel_lo12_nc:ff
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ldrsw x0, [sp,12]
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mov w2, 7
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strb w2, [x1,x0]
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ldr w0, [sp,12]
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add w0, w0, 1
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str w0, [sp,12]
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.L2:
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ldr w0, [sp,12]
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cmp w0, 999
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ble .L3
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mrs x0, tpidr_el0
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add x0, x0, #:tprel_hi12:i
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add x0, x0, #:tprel_lo12_nc:i
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ldr w0, [x0]
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add sp, sp, 16
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ret
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.size main, .-main
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