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https://sourceware.org/git/binutils-gdb.git
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b42f20d2ac
We'll rely on the toolchain probing to determine whether each arch's tests can be run rather the current configure target. This allows testing all of the ports in a multitarget configuration. For now, we don't reformat the files entirely to make it easier to review, and in case we need to make adjustments. Once this feels like it's stable, we can flatten the code a bit by removing the if statement entirely.
169 lines
2.9 KiB
Plaintext
169 lines
2.9 KiB
Plaintext
# mach: frv fr500 fr550
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# sim: --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000
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# xfail: "crashes with bad write" *-*
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; Exit with return code
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.macro exit rc
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setlos.p #1,gr7
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setlos \rc,gr8
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tira gr0,#0
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.endm
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; Pass the test case
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.macro pass
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pass:
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setlos.p #5,gr10
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setlos #1,gr8
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setlos #5,gr7
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sethi.p %hi(passmsg),gr9
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setlo %lo(passmsg),gr9
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tira gr0,#0
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exit #0
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.endm
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; Fail the testcase
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.macro fail
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fail\@:
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setlos.p #5,gr10
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setlos #1,gr8
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setlos #5,gr7
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sethi.p %hi(failmsg),gr9
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setlo %lo(failmsg),gr9
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tira gr0,#0
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exit #1
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.endm
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.data
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failmsg:
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.ascii "fail\n"
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passmsg:
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.ascii "pass\n"
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.text
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.global _start
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_start:
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movsg hsr0,gr10 ; enable insn and data caches
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sethi.p 0xc800,gr11 ; in copy-back mode
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setlo 0x0000,gr11
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or gr10,gr11,gr10
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movgs gr10,hsr0
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sethi.p 0x7,sp
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setlo 0x0000,sp
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; fill the cache
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sethi.p %hi(done1),gr10
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setlo %lo(done1),gr10
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movgs gr10,lr
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setlos.p 0x1000,gr10
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setlos 0x0,gr11
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movgs gr10,lcr
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write1: st.p gr11,@(sp,gr11)
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addi.p gr11,4,gr11
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bctrlr.p 1,0
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bra write1
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done1:
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; read it back
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sethi.p %hi(done2),gr10
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setlo %lo(done2),gr10
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movgs gr10,lr
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setlos.p 0x1000,gr10
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setlos 0x0,gr11
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movgs gr10,lcr
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read1: ld @(sp,gr11),gr12
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cmp gr11,gr12,icc0
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bne icc0,1,fail
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addi.p gr11,4,gr11
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bctrlr.p 1,0
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bra read1
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done2:
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; fill the cache twice
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sethi.p %hi(done3),gr10
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setlo %lo(done3),gr10
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movgs gr10,lr
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setlos.p 0x2000,gr10
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setlos 0x0,gr11
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movgs gr10,lcr
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write3: st.p gr11,@(sp,gr11)
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addi.p gr11,4,gr11
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bctrlr.p 1,0
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bra write3
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done3:
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; read it back
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sethi.p %hi(done4),gr10
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setlo %lo(done4),gr10
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movgs gr10,lr
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setlos.p 0x2000,gr10
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setlos 0x0,gr11
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movgs gr10,lcr
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read4: ld @(sp,gr11),gr12
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cmp gr11,gr12,icc0
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bne icc0,1,fail
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addi.p gr11,4,gr11
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bctrlr.p 1,0
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bra read4
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done4:
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; read it back in reverse
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sethi.p %hi(done5),gr10
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setlo %lo(done5),gr10
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movgs gr10,lr
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setlos.p 0x2000,gr10
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setlos 0x7ffc,gr11
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movgs gr10,lcr
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read5: ld @(sp,gr11),gr12
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cmp gr11,gr12,icc0
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bne icc0,1,fail
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subi.p gr11,4,gr11
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bctrlr.p 1,0
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bra read5
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done5:
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; access data and insns in non-cache areas
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sethi.p 0x8038,gr11 ; bctrlr 0,0
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setlo 0x2000,gr11
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sethi.p 0xff00,gr10 ; documented area
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setlo 0x0000,gr10
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sti gr11,@(gr10,0)
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jmpl @(gr10,gr0)
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; enable RAM mode
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movsg hsr0,gr10
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sethi.p 0x0040,gr12
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setlo 0x0000,gr12
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or gr10,gr12,gr10
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movgs gr10,hsr0
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sethi.p 0xfe00,gr10 ; documented area
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setlo 0x0400,gr10
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sti gr11,@(gr10,0)
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jmpl @(gr10,gr0)
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sethi.p 0xfe40,gr10 ; documented area
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setlo 0x0400,gr10
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sti gr11,@(gr10,0)
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dcf @(gr10,gr0)
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jmpl @(gr10,gr0)
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sethi.p 0x0007,gr10 ; non RAM area
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setlo 0x0000,gr10
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sti gr11,@(gr10,0)
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jmpl @(gr10,gr0)
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sethi.p 0xfe00,gr10 ; insn RAM area
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setlo 0x0000,gr10
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sti gr11,@(gr10,0)
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jmpl @(gr10,gr0)
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sethi.p 0xfe40,gr10 ; data RAM area
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setlo 0x0000,gr10
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sti gr11,@(gr10,0)
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dcf @(gr10,gr0)
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jmpl @(gr10,gr0)
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pass
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fail:
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fail
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