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1061 lines
28 KiB
C
1061 lines
28 KiB
C
/* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
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Copyright (C) 1996, 1997 Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include <ctype.h>
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#include "as.h"
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#include "subsegs.h"
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#include "cgen-opc.h"
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/* Non-null if last insn was a 16 bit insn on a 32 bit boundary
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(i.e. was the first of two 16 bit insns). */
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static const struct cgen_insn *prev_insn = NULL;
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/* Non-zero if we've seen a relaxable insn since the last 32 bit
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alignment request. */
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static int seen_relaxable_p = 0;
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/* Non-zero if -relax specified, in which case sufficient relocs are output
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for the linker to do relaxing.
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We do simple forms of relaxing internally, but they are always done.
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This flag does not apply to them. */
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static int m32r_relax;
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/* If non-NULL, pointer to cpu description file to read.
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This allows runtime additions to the assembler. */
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static char *m32r_cpu_desc;
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/* Non-zero if -m32rx has been specified, in which case support for the
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extended M32RX instruction set should be enabled. */
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/* Indicates the target BFD machine number. */
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static int enable_m32rx = 0;
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/* stuff for .scomm symbols. */
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static segT sbss_section;
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static asection scom_section;
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static asymbol scom_symbol;
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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/* Relocations against symbols are done in two
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parts, with a HI relocation and a LO relocation. Each relocation
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has only 16 bits of space to store an addend. This means that in
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order for the linker to handle carries correctly, it must be able
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to locate both the HI and the LO relocation. This means that the
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relocations must appear in order in the relocation table.
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In order to implement this, we keep track of each unmatched HI
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relocation. We then sort them so that they immediately precede the
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corresponding LO relocation. */
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struct m32r_hi_fixup
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{
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/* Next HI fixup. */
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struct m32r_hi_fixup *next;
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/* This fixup. */
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fixS *fixp;
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/* The section this fixup is in. */
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segT seg;
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};
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/* The list of unmatched HI relocs. */
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static struct m32r_hi_fixup *m32r_hi_fixup_list;
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static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
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static void
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allow_m32rx (int on)
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{
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enable_m32rx = on;
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if (stdoutput != NULL)
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
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}
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const char *md_shortopts = "";
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struct option md_longopts[] =
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{
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#define OPTION_M32RX (OPTION_MD_BASE)
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{"m32rx", no_argument, NULL, OPTION_M32RX},
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#if 0 /* not supported yet */
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#define OPTION_RELAX (OPTION_MD_BASE + 1)
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{"relax", no_argument, NULL, OPTION_RELAX},
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#define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
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{"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
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#endif
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof(md_longopts);
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int
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md_parse_option (c, arg)
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int c;
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char *arg;
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{
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switch (c)
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{
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case OPTION_M32RX:
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allow_m32rx (1);
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break;
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#if 0 /* not supported yet */
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case OPTION_RELAX:
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m32r_relax = 1;
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break;
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case OPTION_CPU_DESC:
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m32r_cpu_desc = arg;
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break;
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#endif
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default:
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return 0;
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}
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return 1;
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}
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void
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md_show_usage (stream)
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FILE *stream;
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{
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fprintf (stream, "M32R/X options:\n");
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fprintf (stream, "\
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--m32rx support the extended m32rx instruction set\n");
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#if 0
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fprintf (stream, "\
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--relax create linker relaxable code\n");
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fprintf (stream, "\
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--cpu-desc provide runtime cpu description file\n");
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#endif
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}
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static void fill_insn PARAMS ((int));
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static void m32r_scomm PARAMS ((int));
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/* Set by md_assemble for use by m32r_fill_insn. */
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static subsegT prev_subseg;
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static segT prev_seg;
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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{
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{ "word", cons, 4 },
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{ "fillinsn", fill_insn, 0 },
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{ "scomm", m32r_scomm, 0 },
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{ "m32r", allow_m32rx, 0},
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{ "m32rx", allow_m32rx, 1},
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{ NULL, NULL, 0 }
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};
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/* FIXME: Should be machine generated. */
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#define NOP_INSN 0x7000
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#define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
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/* When we align the .text section, insert the correct NOP pattern.
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N is the power of 2 alignment. LEN is the length of pattern FILL.
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MAX is the maximum number of characters to skip when doing the alignment,
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or 0 if there is no maximum. */
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int
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m32r_do_align (n, fill, len, max)
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int n;
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const char *fill;
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int len;
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int max;
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{
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if ((fill == NULL || (*fill == 0 && len == 1))
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&& (now_seg->flags & SEC_CODE) != 0
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/* Only do this special handling if aligning to at least a
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4 byte boundary. */
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&& n > 1
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/* Only do this special handling if we're allowed to emit at
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least two bytes. */
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&& (max == 0 || max > 1))
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{
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static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
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#if 0
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/* First align to a 2 byte boundary, in case there is an odd .byte. */
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/* FIXME: How much memory will cause gas to use when assembling a big
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program? Perhaps we can avoid the frag_align call? */
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frag_align (1, 0, 0);
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#endif
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/* Next align to a 4 byte boundary (we know n >= 2) using a parallel
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nop. */
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frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
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/* If doing larger alignments use a repeating sequence of appropriate
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nops. */
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if (n > 2)
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{
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static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
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frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
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max ? max - 2 : 0);
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}
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return 1;
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}
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return 0;
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}
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static void
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assemble_nop (opcode)
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int opcode;
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{
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char *f = frag_more (2);
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md_number_to_chars (f, opcode, 2);
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}
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/* If the last instruction was the first of 2 16 bit insns,
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output a nop to move the PC to a 32 bit boundary.
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This is done via an alignment specification since branch relaxing
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may make it unnecessary.
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Internally, we need to output one of these each time a 32 bit insn is
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seen after an insn that is relaxable. */
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static void
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fill_insn (ignore)
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int ignore;
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{
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(void) m32r_do_align (2, NULL, 0, 0);
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prev_insn = NULL;
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seen_relaxable_p = 0;
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}
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/* Cover function to fill_insn called after a label and at end of assembly.
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The result is always 1: we're called in a conditional to see if the
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current line is a label. */
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int
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m32r_fill_insn (done)
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int done;
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{
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segT seg;
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subsegT subseg;
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if (prev_seg != NULL)
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{
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seg = now_seg;
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subseg = now_subseg;
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subseg_set (prev_seg, prev_subseg);
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fill_insn (0);
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subseg_set (seg, subseg);
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}
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return 1;
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}
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void
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md_begin ()
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{
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flagword applicable;
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segT seg;
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subsegT subseg;
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/* Initialize the `cgen' interface. */
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/* This is a callback from cgen to gas to parse operands. */
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cgen_parse_operand_fn = cgen_parse_operand;
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/* Set the machine number and endian. */
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CGEN_SYM (init_asm) (0 /* mach number */,
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target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
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#if 0 /* not supported yet */
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/* If a runtime cpu description file was provided, parse it. */
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if (m32r_cpu_desc != NULL)
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{
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const char *errmsg;
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errmsg = cgen_read_cpu_file (m32r_cpu_desc);
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if (errmsg != NULL)
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as_bad ("%s: %s", m32r_cpu_desc, errmsg);
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}
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#endif
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/* Save the current subseg so we can restore it [it's the default one and
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we don't want the initial section to be .sbss. */
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seg = now_seg;
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subseg = now_subseg;
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/* The sbss section is for local .scomm symbols. */
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sbss_section = subseg_new (".sbss", 0);
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/* This is copied from perform_an_assembly_pass. */
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applicable = bfd_applicable_section_flags (stdoutput);
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bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
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#if 0 /* What does this do? [see perform_an_assembly_pass] */
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seg_info (bss_section)->bss = 1;
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#endif
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subseg_set (seg, subseg);
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/* We must construct a fake section similar to bfd_com_section
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but with the name .scommon. */
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scom_section = bfd_com_section;
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scom_section.name = ".scommon";
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scom_section.output_section = &scom_section;
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scom_section.symbol = &scom_symbol;
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scom_section.symbol_ptr_ptr = &scom_section.symbol;
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scom_symbol = *bfd_com_section.symbol;
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scom_symbol.name = ".scommon";
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scom_symbol.section = &scom_section;
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allow_m32rx (enable_m32rx);
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}
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void
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md_assemble (str)
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char *str;
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{
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#ifdef CGEN_INT_INSN
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cgen_insn_t buffer[CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
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#else
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char buffer[CGEN_MAX_INSN_SIZE];
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#endif
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struct cgen_fields fields;
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const struct cgen_insn *insn;
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char *errmsg;
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/* Initialize GAS's cgen interface for a new instruction. */
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cgen_asm_init_parse ();
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insn = CGEN_SYM (assemble_insn) (str, &fields, buffer, &errmsg);
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if (!insn)
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{
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as_bad (errmsg);
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return;
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}
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if (CGEN_INSN_BITSIZE (insn) == 32)
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{
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/* 32 bit insns must live on 32 bit boundaries. */
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/* FIXME: If calling fill_insn too many times turns us into a memory
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pig, can we call assemble_nop instead of !seen_relaxable_p? */
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if (prev_insn || seen_relaxable_p)
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fill_insn (0);
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cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
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}
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else
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{
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/* Keep track of whether we've seen a pair of 16 bit insns.
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PREV_INSN is NULL when we're on a 32 bit boundary. */
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if (prev_insn)
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prev_insn = NULL;
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else
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prev_insn = insn;
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cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
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/* If the insn needs the following one to be on a 32 bit boundary
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(e.g. subroutine calls), fill this insn's slot. */
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if (prev_insn
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&& CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
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fill_insn (0);
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}
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/* If this is a relaxable insn (can be replaced with a larger version)
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mark the fact so that we can emit an alignment directive for a following
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32 bit insn if we see one. */
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if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
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seen_relaxable_p = 1;
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/* Set these so m32r_fill_insn can use them. */
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prev_seg = now_seg;
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prev_subseg = now_subseg;
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}
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/* The syntax in the manual says constants begin with '#'.
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We just ignore it. */
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void
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md_operand (expressionP)
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expressionS *expressionP;
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{
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if (*input_line_pointer == '#')
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{
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input_line_pointer++;
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expression (expressionP);
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}
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}
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valueT
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md_section_align (segment, size)
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segT segment;
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valueT size;
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{
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int align = bfd_get_section_alignment (stdoutput, segment);
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return ((size + (1 << align) - 1) & (-1 << align));
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}
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symbolS *
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md_undefined_symbol (name)
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char *name;
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{
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return 0;
|
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}
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|
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/* .scomm pseudo-op handler.
|
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This is a new pseudo-op to handle putting objects in .scommon.
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By doing this the linker won't need to do any work and more importantly
|
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it removes the implicit -G arg necessary to correctly link the object file.
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*/
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static void
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m32r_scomm (ignore)
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int ignore;
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{
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register char *name;
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register char c;
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register char *p;
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offsetT size;
|
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register symbolS *symbolP;
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||
offsetT align;
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int align2;
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name = input_line_pointer;
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c = get_symbol_end ();
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/* just after name is now '\0' */
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p = input_line_pointer;
|
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*p = c;
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SKIP_WHITESPACE ();
|
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if (*input_line_pointer != ',')
|
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{
|
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as_bad ("Expected comma after symbol-name: rest of line ignored.");
|
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ignore_rest_of_line ();
|
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return;
|
||
}
|
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|
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input_line_pointer++; /* skip ',' */
|
||
if ((size = get_absolute_expression ()) < 0)
|
||
{
|
||
as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
|
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ignore_rest_of_line ();
|
||
return;
|
||
}
|
||
|
||
/* The third argument to .scomm is the alignment. */
|
||
if (*input_line_pointer != ',')
|
||
align = 8;
|
||
else
|
||
{
|
||
++input_line_pointer;
|
||
align = get_absolute_expression ();
|
||
if (align <= 0)
|
||
{
|
||
as_warn ("ignoring bad alignment");
|
||
align = 8;
|
||
}
|
||
}
|
||
/* Convert to a power of 2 alignment. */
|
||
if (align)
|
||
{
|
||
for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
|
||
continue;
|
||
if (align != 1)
|
||
{
|
||
as_bad ("Common alignment not a power of 2");
|
||
ignore_rest_of_line ();
|
||
return;
|
||
}
|
||
}
|
||
else
|
||
align2 = 0;
|
||
|
||
*p = 0;
|
||
symbolP = symbol_find_or_make (name);
|
||
*p = c;
|
||
|
||
if (S_IS_DEFINED (symbolP))
|
||
{
|
||
as_bad ("Ignoring attempt to re-define symbol `%s'.",
|
||
S_GET_NAME (symbolP));
|
||
ignore_rest_of_line ();
|
||
return;
|
||
}
|
||
|
||
if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
|
||
{
|
||
as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
|
||
S_GET_NAME (symbolP),
|
||
(long) S_GET_VALUE (symbolP),
|
||
(long) size);
|
||
|
||
ignore_rest_of_line ();
|
||
return;
|
||
}
|
||
|
||
if (symbolP->local)
|
||
{
|
||
segT old_sec = now_seg;
|
||
int old_subsec = now_subseg;
|
||
char *pfrag;
|
||
|
||
record_alignment (sbss_section, align2);
|
||
subseg_set (sbss_section, 0);
|
||
if (align2)
|
||
frag_align (align2, 0, 0);
|
||
if (S_GET_SEGMENT (symbolP) == sbss_section)
|
||
symbolP->sy_frag->fr_symbol = 0;
|
||
symbolP->sy_frag = frag_now;
|
||
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
|
||
(char *) 0);
|
||
*pfrag = 0;
|
||
S_SET_SIZE (symbolP, size);
|
||
S_SET_SEGMENT (symbolP, sbss_section);
|
||
S_CLEAR_EXTERNAL (symbolP);
|
||
subseg_set (old_sec, old_subsec);
|
||
}
|
||
else
|
||
{
|
||
S_SET_VALUE (symbolP, (valueT) size);
|
||
S_SET_ALIGN (symbolP, align2);
|
||
S_SET_EXTERNAL (symbolP);
|
||
S_SET_SEGMENT (symbolP, &scom_section);
|
||
}
|
||
|
||
demand_empty_rest_of_line ();
|
||
}
|
||
|
||
/* Interface to relax_segment. */
|
||
|
||
/* FIXME: Build table by hand, get it working, then machine generate. */
|
||
|
||
const relax_typeS md_relax_table[] =
|
||
{
|
||
/* The fields are:
|
||
1) most positive reach of this state,
|
||
2) most negative reach of this state,
|
||
3) how many bytes this mode will add to the size of the current frag
|
||
4) which index into the table to try if we can't fit into this one. */
|
||
|
||
/* The first entry must be unused because an `rlx_more' value of zero ends
|
||
each list. */
|
||
{1, 1, 0, 0},
|
||
|
||
/* The displacement used by GAS is from the end of the 2 byte insn,
|
||
so we subtract 2 from the following. */
|
||
/* 16 bit insn, 8 bit disp -> 10 bit range.
|
||
This doesn't handle a branch in the right slot at the border:
|
||
the "& -4" isn't taken into account. It's not important enough to
|
||
complicate things over it, so we subtract an extra 2 (or + 2 in -ve
|
||
case). */
|
||
{511 - 2 - 2, -512 - 2 + 2, 0, 2 },
|
||
/* 32 bit insn, 24 bit disp -> 26 bit range. */
|
||
{0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
|
||
/* Same thing, but with leading nop for alignment. */
|
||
{0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
|
||
};
|
||
|
||
long
|
||
m32r_relax_frag (fragP, stretch)
|
||
fragS *fragP;
|
||
long stretch;
|
||
{
|
||
/* Address of branch insn. */
|
||
long address = fragP->fr_address + fragP->fr_fix - 2;
|
||
long growth = 0;
|
||
|
||
/* Keep 32 bit insns aligned on 32 bit boundaries. */
|
||
if (fragP->fr_subtype == 2)
|
||
{
|
||
if ((address & 3) != 0)
|
||
{
|
||
fragP->fr_subtype = 3;
|
||
growth = 2;
|
||
}
|
||
}
|
||
else if (fragP->fr_subtype == 3)
|
||
{
|
||
if ((address & 3) == 0)
|
||
{
|
||
fragP->fr_subtype = 2;
|
||
growth = -2;
|
||
}
|
||
}
|
||
else
|
||
{
|
||
growth = relax_frag (fragP, stretch);
|
||
|
||
/* Long jump on odd halfword boundary? */
|
||
if (fragP->fr_subtype == 2 && (address & 3) != 0)
|
||
{
|
||
fragP->fr_subtype = 3;
|
||
growth += 2;
|
||
}
|
||
}
|
||
|
||
return growth;
|
||
}
|
||
|
||
/* Return an initial guess of the length by which a fragment must grow to
|
||
hold a branch to reach its destination.
|
||
Also updates fr_type/fr_subtype as necessary.
|
||
|
||
Called just before doing relaxation.
|
||
Any symbol that is now undefined will not become defined.
|
||
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
|
||
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
|
||
Although it may not be explicit in the frag, pretend fr_var starts with a
|
||
0 value. */
|
||
|
||
int
|
||
md_estimate_size_before_relax (fragP, segment)
|
||
fragS *fragP;
|
||
segT segment;
|
||
{
|
||
int old_fr_fix = fragP->fr_fix;
|
||
char *opcode = fragP->fr_opcode;
|
||
|
||
/* The only thing we have to handle here are symbols outside of the
|
||
current segment. They may be undefined or in a different segment in
|
||
which case linker scripts may place them anywhere.
|
||
However, we can't finish the fragment here and emit the reloc as insn
|
||
alignment requirements may move the insn about. */
|
||
|
||
if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
|
||
{
|
||
/* The symbol is undefined in this segment.
|
||
Change the relaxation subtype to the max allowable and leave
|
||
all further handling to md_convert_frag. */
|
||
fragP->fr_subtype = 2;
|
||
|
||
#if 0 /* Can't use this, but leave in for illustration. */
|
||
/* Change 16 bit insn to 32 bit insn. */
|
||
opcode[0] |= 0x80;
|
||
|
||
/* Increase known (fixed) size of fragment. */
|
||
fragP->fr_fix += 2;
|
||
|
||
/* Create a relocation for it. */
|
||
fix_new (fragP, old_fr_fix, 4,
|
||
fragP->fr_symbol,
|
||
fragP->fr_offset, 1 /* pcrel */,
|
||
/* FIXME: Can't use a real BFD reloc here.
|
||
cgen_md_apply_fix3 can't handle it. */
|
||
BFD_RELOC_M32R_26_PCREL);
|
||
|
||
/* Mark this fragment as finished. */
|
||
frag_wane (fragP);
|
||
#else
|
||
{
|
||
const struct cgen_insn *insn;
|
||
int i;
|
||
|
||
/* Update the recorded insn.
|
||
Fortunately we don't have to look very far.
|
||
FIXME: Change this to record in the instruction the next higher
|
||
relaxable insn to use. */
|
||
for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
|
||
{
|
||
if ((strcmp (CGEN_INSN_SYNTAX (insn)->mnemonic,
|
||
CGEN_INSN_SYNTAX (fragP->fr_cgen.insn)->mnemonic)
|
||
== 0)
|
||
&& CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
|
||
break;
|
||
}
|
||
if (i == 4)
|
||
abort ();
|
||
fragP->fr_cgen.insn = insn;
|
||
return 2;
|
||
}
|
||
#endif
|
||
}
|
||
|
||
return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
|
||
}
|
||
|
||
/* *fragP has been relaxed to its final size, and now needs to have
|
||
the bytes inside it modified to conform to the new size.
|
||
|
||
Called after relaxation is finished.
|
||
fragP->fr_type == rs_machine_dependent.
|
||
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
||
|
||
void
|
||
md_convert_frag (abfd, sec, fragP)
|
||
bfd *abfd;
|
||
segT sec;
|
||
fragS *fragP;
|
||
{
|
||
char *opcode, *displacement;
|
||
int target_address, opcode_address, extension, addend;
|
||
|
||
opcode = fragP->fr_opcode;
|
||
|
||
/* Address opcode resides at in file space. */
|
||
opcode_address = fragP->fr_address + fragP->fr_fix - 2;
|
||
|
||
switch (fragP->fr_subtype)
|
||
{
|
||
case 1 :
|
||
extension = 0;
|
||
displacement = &opcode[1];
|
||
break;
|
||
case 2 :
|
||
opcode[0] |= 0x80;
|
||
extension = 2;
|
||
displacement = &opcode[1];
|
||
break;
|
||
case 3 :
|
||
opcode[2] = opcode[0] | 0x80;
|
||
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
|
||
opcode_address += 2;
|
||
extension = 4;
|
||
displacement = &opcode[3];
|
||
break;
|
||
default :
|
||
abort ();
|
||
}
|
||
|
||
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
|
||
{
|
||
/* symbol must be resolved by linker */
|
||
if (fragP->fr_offset & 3)
|
||
as_warn ("Addend to unresolved symbol not on word boundary.");
|
||
addend = fragP->fr_offset >> 2;
|
||
}
|
||
else
|
||
{
|
||
/* Address we want to reach in file space. */
|
||
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
|
||
target_address += fragP->fr_symbol->sy_frag->fr_address;
|
||
addend = (target_address - (opcode_address & -4)) >> 2;
|
||
}
|
||
|
||
/* Create a relocation for symbols that must be resolved by the linker.
|
||
Otherwise output the completed insn. */
|
||
|
||
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
|
||
{
|
||
assert (fragP->fr_subtype != 1);
|
||
assert (fragP->fr_cgen.insn != 0);
|
||
cgen_record_fixup (fragP,
|
||
/* Offset of branch insn in frag. */
|
||
fragP->fr_fix + extension - 4,
|
||
fragP->fr_cgen.insn,
|
||
4 /*length*/,
|
||
/* FIXME: quick hack */
|
||
#if 0
|
||
CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
|
||
#else
|
||
CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
|
||
#endif
|
||
fragP->fr_cgen.opinfo,
|
||
fragP->fr_symbol, fragP->fr_offset);
|
||
}
|
||
|
||
#define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
|
||
|
||
md_number_to_chars (displacement, (valueT) addend,
|
||
SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
|
||
|
||
fragP->fr_fix += extension;
|
||
}
|
||
|
||
/* Functions concerning relocs. */
|
||
|
||
/* The location from which a PC relative jump should be calculated,
|
||
given a PC relative reloc. */
|
||
|
||
long
|
||
md_pcrel_from_section (fixP, sec)
|
||
fixS *fixP;
|
||
segT sec;
|
||
{
|
||
if (fixP->fx_addsy != (symbolS *) NULL
|
||
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
||
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
|
||
{
|
||
/* The symbol is undefined (or is defined but not in this section).
|
||
Let the linker figure it out. */
|
||
return 0;
|
||
}
|
||
|
||
return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
|
||
}
|
||
|
||
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
||
Returns BFD_RELOC_NONE if no reloc type can be found.
|
||
*FIXP may be modified if desired. */
|
||
|
||
bfd_reloc_code_real_type
|
||
CGEN_SYM (lookup_reloc) (insn, operand, fixP)
|
||
const struct cgen_insn *insn;
|
||
const struct cgen_operand *operand;
|
||
fixS *fixP;
|
||
{
|
||
switch (CGEN_OPERAND_TYPE (operand))
|
||
{
|
||
case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
|
||
case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
|
||
case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
|
||
case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
|
||
case M32R_OPERAND_HI16 :
|
||
case M32R_OPERAND_SLO16 :
|
||
case M32R_OPERAND_ULO16 :
|
||
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
||
if (fixP->tc_fix_data.opinfo != 0)
|
||
return fixP->tc_fix_data.opinfo;
|
||
break;
|
||
}
|
||
return BFD_RELOC_NONE;
|
||
}
|
||
|
||
/* Called while parsing an instruction to create a fixup.
|
||
We need to check for HI16 relocs and queue them up for later sorting. */
|
||
|
||
fixS *
|
||
m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
|
||
fragS *frag;
|
||
int where;
|
||
const struct cgen_insn *insn;
|
||
int length;
|
||
const struct cgen_operand *operand;
|
||
int opinfo;
|
||
expressionS *exp;
|
||
{
|
||
fixS *fixP = cgen_record_fixup_exp (frag, where, insn, length,
|
||
operand, opinfo, exp);
|
||
|
||
switch (CGEN_OPERAND_TYPE (operand))
|
||
{
|
||
case M32R_OPERAND_HI16 :
|
||
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
||
if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
|
||
|| fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
||
m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
|
||
break;
|
||
}
|
||
|
||
return fixP;
|
||
}
|
||
|
||
/* Record a HI16 reloc for later matching with its LO16 cousin. */
|
||
|
||
static void
|
||
m32r_record_hi16 (reloc_type, fixP, seg)
|
||
int reloc_type;
|
||
fixS *fixP;
|
||
segT seg;
|
||
{
|
||
struct m32r_hi_fixup *hi_fixup;
|
||
|
||
assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
|
||
|| reloc_type == BFD_RELOC_M32R_HI16_ULO);
|
||
|
||
hi_fixup = ((struct m32r_hi_fixup *)
|
||
xmalloc (sizeof (struct m32r_hi_fixup)));
|
||
hi_fixup->fixp = fixP;
|
||
hi_fixup->seg = now_seg;
|
||
hi_fixup->next = m32r_hi_fixup_list;
|
||
m32r_hi_fixup_list = hi_fixup;
|
||
}
|
||
|
||
/* Return BFD reloc type from opinfo field in a fixS.
|
||
It's tricky using fx_r_type in m32r_frob_file because the values
|
||
are BFD_RELOC_UNUSED + operand number. */
|
||
#define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
|
||
|
||
/* Sort any unmatched HI16 relocs so that they immediately precede
|
||
the corresponding LO16 reloc. This is called before md_apply_fix and
|
||
tc_gen_reloc. */
|
||
|
||
void
|
||
m32r_frob_file ()
|
||
{
|
||
struct m32r_hi_fixup *l;
|
||
|
||
for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
|
||
{
|
||
segment_info_type *seginfo;
|
||
int pass;
|
||
|
||
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
|
||
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
|
||
|
||
/* Check quickly whether the next fixup happens to be a matching low. */
|
||
if (l->fixp->fx_next != NULL
|
||
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
|
||
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
||
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
||
continue;
|
||
|
||
/* Look through the fixups for this segment for a matching `low'.
|
||
When we find one, move the high/shigh just in front of it. We do
|
||
this in two passes. In the first pass, we try to find a
|
||
unique `low'. In the second pass, we permit multiple high's
|
||
relocs for a single `low'. */
|
||
seginfo = seg_info (l->seg);
|
||
for (pass = 0; pass < 2; pass++)
|
||
{
|
||
fixS *f, *prev;
|
||
|
||
prev = NULL;
|
||
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
||
{
|
||
/* Check whether this is a `low' fixup which matches l->fixp. */
|
||
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
|
||
&& f->fx_addsy == l->fixp->fx_addsy
|
||
&& f->fx_offset == l->fixp->fx_offset
|
||
&& (pass == 1
|
||
|| prev == NULL
|
||
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
|
||
&& FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
|
||
|| prev->fx_addsy != f->fx_addsy
|
||
|| prev->fx_offset != f->fx_offset))
|
||
{
|
||
fixS **pf;
|
||
|
||
/* Move l->fixp before f. */
|
||
for (pf = &seginfo->fix_root;
|
||
*pf != l->fixp;
|
||
pf = &(*pf)->fx_next)
|
||
assert (*pf != NULL);
|
||
|
||
*pf = l->fixp->fx_next;
|
||
|
||
l->fixp->fx_next = f;
|
||
if (prev == NULL)
|
||
seginfo->fix_root = l->fixp;
|
||
else
|
||
prev->fx_next = l->fixp;
|
||
|
||
break;
|
||
}
|
||
|
||
prev = f;
|
||
}
|
||
|
||
if (f != NULL)
|
||
break;
|
||
|
||
if (pass == 1)
|
||
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
||
"Unmatched high/shigh reloc");
|
||
}
|
||
}
|
||
}
|
||
|
||
/* See whether we need to force a relocation into the output file.
|
||
This is used to force out switch and PC relative relocations when
|
||
relaxing. */
|
||
|
||
int
|
||
m32r_force_relocation (fix)
|
||
fixS *fix;
|
||
{
|
||
if (! m32r_relax)
|
||
return 0;
|
||
|
||
return (fix->fx_pcrel
|
||
|| 0 /* ??? */);
|
||
}
|
||
|
||
/* Write a value out to the object file, using the appropriate endianness. */
|
||
|
||
void
|
||
md_number_to_chars (buf, val, n)
|
||
char *buf;
|
||
valueT val;
|
||
int n;
|
||
{
|
||
if (target_big_endian)
|
||
number_to_chars_bigendian (buf, val, n);
|
||
else
|
||
number_to_chars_littleendian (buf, val, n);
|
||
}
|
||
|
||
/* Turn a string in input_line_pointer into a floating point constant of type
|
||
type, and store the appropriate bytes in *litP. The number of LITTLENUMS
|
||
emitted is stored in *sizeP . An error message is returned, or NULL on OK.
|
||
*/
|
||
|
||
/* Equal to MAX_PRECISION in atof-ieee.c */
|
||
#define MAX_LITTLENUMS 6
|
||
|
||
char *
|
||
md_atof (type, litP, sizeP)
|
||
char type;
|
||
char *litP;
|
||
int *sizeP;
|
||
{
|
||
int i,prec;
|
||
LITTLENUM_TYPE words[MAX_LITTLENUMS];
|
||
LITTLENUM_TYPE *wordP;
|
||
char *t;
|
||
char *atof_ieee ();
|
||
|
||
switch (type)
|
||
{
|
||
case 'f':
|
||
case 'F':
|
||
case 's':
|
||
case 'S':
|
||
prec = 2;
|
||
break;
|
||
|
||
case 'd':
|
||
case 'D':
|
||
case 'r':
|
||
case 'R':
|
||
prec = 4;
|
||
break;
|
||
|
||
/* FIXME: Some targets allow other format chars for bigger sizes here. */
|
||
|
||
default:
|
||
*sizeP = 0;
|
||
return "Bad call to md_atof()";
|
||
}
|
||
|
||
t = atof_ieee (input_line_pointer, type, words);
|
||
if (t)
|
||
input_line_pointer = t;
|
||
*sizeP = prec * sizeof (LITTLENUM_TYPE);
|
||
|
||
if (target_big_endian)
|
||
{
|
||
for (i = 0; i < prec; i++)
|
||
{
|
||
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
|
||
litP += sizeof (LITTLENUM_TYPE);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
for (i = prec - 1; i >= 0; i--)
|
||
{
|
||
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
|
||
litP += sizeof (LITTLENUM_TYPE);
|
||
}
|
||
}
|
||
|
||
return 0;
|
||
}
|