Tsukasa OI b9593cb705 sim/riscv: Complete tidying up with SBREAK ... This commit removes SBREAK-related references on the simulator as it's renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1). sim/ChangeLog: * riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".		2022-09-05 09:42:06 +01:00
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aarch64
arm
avr
bfin
bpf
common
cr16
cris
d10v
erc32	sim/erc32: fix gdb with simulator build	2022-09-04 18:02:15 +01:00
example-synacor
frv
ft32
h8300
igen
iq2000
lm32
m4
m32c
m32r
m68hc11
mcore
microblaze
mips
mn10300
moxie
msp430
or1k
ppc
pru
riscv	sim/riscv: Complete tidying up with SBREAK	2022-09-05 09:42:06 +01:00
rl78
rx
sh
testsuite
v850
.gitignore
aclocal.m4
arch-subdir.mk.in
ChangeLog-2021
config.h.in
configure
configure.ac
COPYING
gdbinit.in
MAINTAINERS	sim: Update mailing list address	2022-09-01 10:15:09 -04:00
Makefile.am
Makefile.in
README-HACKING