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201 lines
7.3 KiB
C
201 lines
7.3 KiB
C
/* Copyright (C) 2009-2021 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef NAT_AARCH64_LINUX_HW_POINT_H
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#define NAT_AARCH64_LINUX_HW_POINT_H
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#include "gdbsupport/break-common.h" /* For enum target_hw_bp_type. */
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/* Macro definitions, data structures, and code for the hardware
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breakpoint and hardware watchpoint support follow. We use the
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following abbreviations throughout the code:
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hw - hardware
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bp - breakpoint
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wp - watchpoint */
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/* Maximum number of hardware breakpoint and watchpoint registers.
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Neither of these values may exceed the width of dr_changed_t
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measured in bits. */
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#define AARCH64_HBP_MAX_NUM 16
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#define AARCH64_HWP_MAX_NUM 16
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/* Alignment requirement in bytes for addresses written to
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hardware breakpoint and watchpoint value registers.
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A ptrace call attempting to set an address that does not meet the
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alignment criteria will fail. Limited support has been provided in
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this port for unaligned watchpoints, such that from a GDB user
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perspective, an unaligned watchpoint may be requested.
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This is achieved by minimally enlarging the watched area to meet the
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alignment requirement, and if necessary, splitting the watchpoint
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over several hardware watchpoint registers. */
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#define AARCH64_HBP_ALIGNMENT 4
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#define AARCH64_HWP_ALIGNMENT 8
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/* The maximum length of a memory region that can be watched by one
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hardware watchpoint register. */
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#define AARCH64_HWP_MAX_LEN_PER_REG 8
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/* ptrace hardware breakpoint resource info is formatted as follows:
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31 24 16 8 0
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+---------------+--------------+---------------+---------------+
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| RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
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+---------------+--------------+---------------+---------------+ */
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/* Macros to extract fields from the hardware debug information word. */
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#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
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#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
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/* Macro for the expected version of the ARMv8-A debug architecture. */
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#define AARCH64_DEBUG_ARCH_V8 0x6
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#define AARCH64_DEBUG_ARCH_V8_1 0x7
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#define AARCH64_DEBUG_ARCH_V8_2 0x8
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/* ptrace expects control registers to be formatted as follows:
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31 13 5 3 1 0
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+--------------------------------+----------+------+------+----+
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| RESERVED (SBZ) | MASK | TYPE | PRIV | EN |
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+--------------------------------+----------+------+------+----+
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The TYPE field is ignored for breakpoints. */
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#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
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#define DR_CONTROL_MASK(ctrl) (((ctrl) >> 5) & 0xff)
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/* Each bit of a variable of this type is used to indicate whether a
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hardware breakpoint or watchpoint setting has been changed since
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the last update.
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Bit N corresponds to the Nth hardware breakpoint or watchpoint
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setting which is managed in aarch64_debug_reg_state, where N is
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valid between 0 and the total number of the hardware breakpoint or
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watchpoint debug registers minus 1.
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When bit N is 1, the corresponding breakpoint or watchpoint setting
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has changed, and therefore the corresponding hardware debug
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register needs to be updated via the ptrace interface.
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In the per-thread arch-specific data area, we define two such
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variables for per-thread hardware breakpoint and watchpoint
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settings respectively.
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This type is part of the mechanism which helps reduce the number of
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ptrace calls to the kernel, i.e. avoid asking the kernel to write
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to the debug registers with unchanged values. */
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typedef ULONGEST dr_changed_t;
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/* Set each of the lower M bits of X to 1; assert X is wide enough. */
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#define DR_MARK_ALL_CHANGED(x, m) \
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do \
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{ \
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gdb_assert (sizeof ((x)) * 8 >= (m)); \
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(x) = (((dr_changed_t)1 << (m)) - 1); \
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} while (0)
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#define DR_MARK_N_CHANGED(x, n) \
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do \
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{ \
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(x) |= ((dr_changed_t)1 << (n)); \
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} while (0)
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#define DR_CLEAR_CHANGED(x) \
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do \
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{ \
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(x) = 0; \
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} while (0)
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#define DR_HAS_CHANGED(x) ((x) != 0)
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#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
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/* Structure for managing the hardware breakpoint/watchpoint resources.
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DR_ADDR_* stores the address, DR_CTRL_* stores the control register
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content, and DR_REF_COUNT_* counts the numbers of references to the
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corresponding bp/wp, by which way the limited hardware resources
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are not wasted on duplicated bp/wp settings (though so far gdb has
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done a good job by not sending duplicated bp/wp requests). */
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struct aarch64_debug_reg_state
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{
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/* hardware breakpoint */
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CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
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unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
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unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
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/* hardware watchpoint */
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/* Address aligned down to AARCH64_HWP_ALIGNMENT. */
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CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
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/* Address as entered by user without any forced alignment. */
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CORE_ADDR dr_addr_orig_wp[AARCH64_HWP_MAX_NUM];
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unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
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unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
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};
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/* Per-thread arch-specific data we want to keep. */
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struct arch_lwp_info
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{
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/* When bit N is 1, it indicates the Nth hardware breakpoint or
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watchpoint register pair needs to be updated when the thread is
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resumed; see aarch64_linux_prepare_to_resume. */
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dr_changed_t dr_changed_bp;
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dr_changed_t dr_changed_wp;
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};
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extern int aarch64_num_bp_regs;
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extern int aarch64_num_wp_regs;
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unsigned int aarch64_watchpoint_offset (unsigned int ctrl);
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unsigned int aarch64_watchpoint_length (unsigned int ctrl);
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int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
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int len, int is_insert,
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struct aarch64_debug_reg_state *state);
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int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
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int len, int is_insert,
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struct aarch64_debug_reg_state *state);
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void aarch64_linux_set_debug_regs (struct aarch64_debug_reg_state *state,
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int tid, int watchpoint);
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/* Return TRUE if there are any hardware breakpoints. If WATCHPOINT is TRUE,
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check hardware watchpoints instead. */
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bool aarch64_linux_any_set_debug_regs_state (aarch64_debug_reg_state *state,
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bool watchpoint);
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void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
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const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type);
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void aarch64_linux_get_debug_reg_capacity (int tid);
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struct aarch64_debug_reg_state *aarch64_get_debug_reg_state (pid_t pid);
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int aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr, int len);
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#endif /* NAT_AARCH64_LINUX_HW_POINT_H */
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