mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-09 04:21:49 +08:00
dd74a60337
For the case when NDD and NF are both 0 in evex-promoted format,
we will fully support and test it in another patch.
gas/ChangeLog:
* NEWS: Support Intel APX NF.
* config/tc-i386.c (enum i386_error): Add unsupported_nf.
(struct _i386_insn): Add has_nf.
(is_apx_evex_encoding): Ditto.
(build_apx_evex_prefix): Encode the NF bit.
(md_assemble): Handle unsupported_nf.
(parse_insn): Handle Prefix_NF and report bad for illegal combination.
(can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf.
(match_template): Support D for APX_F insns and check NF support.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add apx nf tests.
* testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
* testsuite/gas/i386/x86-64-apx-nf.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Add %NF to the instructions that support APX NF and
add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
* i386-dis-evex-reg.h: Ditto.
* i386-dis.c (struct instr_info): Add nf.
(struct dis386): Add "NF" for EVEX.NF.
(get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case.
(print_insn): Handle ins.vex.nf.
(putop): Handle "%NF".
* i386-opc.h (Prefix_NF): New.
* i386-opc.tbl: Added new entries to support full APX NF instructions.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Regenerated.
123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/* REG_EVEX_0F71 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "%XEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ Bad_Opcode },
|
|
{ "%XEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ Bad_Opcode },
|
|
{ "%XEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
},
|
|
/* REG_EVEX_0F72 */
|
|
{
|
|
{ "vpror%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ VEX_W_TABLE (EVEX_W_0F72_R_2) },
|
|
{ Bad_Opcode },
|
|
{ "%XEvpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_0F72_R_6) },
|
|
},
|
|
/* REG_EVEX_0F73 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_0F73_R_2) },
|
|
{ "%XEvpsrldqY", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_0F73_R_6) },
|
|
{ "%XEvpslldqY", { Vex, EXx, Ib }, PREFIX_DATA },
|
|
},
|
|
/* REG_EVEX_0F38C6_L_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vgatherpf0dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
|
|
{ "vgatherpf1dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vscatterpf0dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
|
|
{ "vscatterpf1dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
|
|
},
|
|
/* REG_EVEX_0F38C7_L_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vgatherpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
|
|
{ "vgatherpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
|
|
{ "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
|
|
},
|
|
/* REG_EVEX_MAP4_80 */
|
|
{
|
|
{ "%NFaddA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
{ "%NForA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
{ "adcA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
{ "sbbA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
{ "%NFandA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
{ "%NFsubA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
{ "%NFxorA", { VexGb, Eb, Ib }, NO_PREFIX },
|
|
},
|
|
/* REG_EVEX_MAP4_81 */
|
|
{
|
|
{ "%NFaddQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
{ "%NForQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
{ "adcQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
{ "sbbQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
{ "%NFandQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
{ "%NFsubQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
{ "%NFxorQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
|
},
|
|
/* REG_EVEX_MAP4_83 */
|
|
{
|
|
{ "%NFaddQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
{ "%NForQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
{ "adcQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
{ "sbbQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
{ "%NFandQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
{ "%NFsubQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
{ "%NFxorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
|
},
|
|
/* REG_EVEX_MAP4_8F */
|
|
{
|
|
{ VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) },
|
|
},
|
|
/* REG_EVEX_MAP4_F6 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "notA", { VexGb, Eb }, NO_PREFIX },
|
|
{ "%NFnegA", { VexGb, Eb }, NO_PREFIX },
|
|
{ "%NFmulA", { Eb }, NO_PREFIX },
|
|
{ "%NFimulA", { Eb }, NO_PREFIX },
|
|
{ "%NFdivA", { Eb }, NO_PREFIX },
|
|
{ "%NFidivA", { Eb }, NO_PREFIX },
|
|
},
|
|
/* REG_EVEX_MAP4_F7 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "notQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
|
{ "%NFnegQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
|
{ "%NFmulQ", { Ev }, PREFIX_NP_OR_DATA },
|
|
{ "%NFimulQ", { Ev }, PREFIX_NP_OR_DATA },
|
|
{ "%NFdivQ", { Ev }, PREFIX_NP_OR_DATA },
|
|
{ "%NFidivQ", { Ev }, PREFIX_NP_OR_DATA },
|
|
},
|
|
/* REG_EVEX_MAP4_FE */
|
|
{
|
|
{ "%NFincA", { VexGb, Eb }, NO_PREFIX },
|
|
{ "%NFdecA", { VexGb, Eb }, NO_PREFIX },
|
|
},
|
|
/* REG_EVEX_MAP4_FF */
|
|
{
|
|
{ "%NFincQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
|
{ "%NFdecQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) },
|
|
},
|