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c5e3a3641e
For these three relocations, 17 bit signed value should be used, instead of 16 bit. The bitsize field is changed from 16 to 17, this field in aarch64 backend is used for overflow check only. bfd/ 2016-02-26 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (elfNN_aarch64_howto_table): Fix signed overflow check for MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2. ld/ 2016-02-26 Renlin Li <renlin.li@arm.com> * testsuite/ld-aarch64/aarch64-elf.exp: Run new testcases. * testsuite/ld-aarch64/emit-relocs-270.d: Update to use new boundary. * testsuite/ld-aarch64/emit-relocs-271.d: Likewise. * testsuite/ld-aarch64/emit-relocs-272.d: Likewise. * testsuite/ld-aarch64/emit-relocs-270-overflow.d: New. * testsuite/ld-aarch64/emit-relocs-270-overflow.s: New. * testsuite/ld-aarch64/emit-relocs-271-overflow.d: New. * testsuite/ld-aarch64/emit-relocs-271-overflow.s: New. * testsuite/ld-aarch64/emit-relocs-272-overflow.d: New. * testsuite/ld-aarch64/emit-relocs-272-overflow.s: New.
6 lines
78 B
ArmAsm
6 lines
78 B
ArmAsm
.comm gempy,4,4
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.text
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movz x4, :abs_g1_s:tempy
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movz x5, :abs_g1_s:tempy1
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