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a2c5833233
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
405 lines
16 KiB
Plaintext
405 lines
16 KiB
Plaintext
@c Copyright (C) 1991-2022 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node Z8000-Dependent
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@chapter Z8000 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter Z8000 Dependent Features
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@end ifclear
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@cindex Z8000 support
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The Z8000 @value{AS} supports both members of the Z8000 family: the
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unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
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24 bit addresses.
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When the assembler is in unsegmented mode (specified with the
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@code{unsegm} directive), an address takes up one word (16 bit)
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sized register. When the assembler is in segmented mode (specified with
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the @code{segm} directive), a 24-bit address takes up a long (32 bit)
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register. @xref{Z8000 Directives,,Assembler Directives for the Z8000},
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for a list of other Z8000 specific assembler directives.
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@menu
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* Z8000 Options:: Command-line options for the Z8000
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* Z8000 Syntax:: Assembler syntax for the Z8000
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* Z8000 Directives:: Special directives for the Z8000
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* Z8000 Opcodes:: Opcodes
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@end menu
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@node Z8000 Options
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@section Options
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@cindex Z8000 options
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@cindex options, Z8000
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@table @option
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@cindex @code{-z8001} command-line option, Z8000
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@item -z8001
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Generate segmented code by default.
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@cindex @code{-z8002} command-line option, Z8000
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@item -z8002
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Generate unsegmented code by default.
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@end table
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@node Z8000 Syntax
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@section Syntax
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@menu
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* Z8000-Chars:: Special Characters
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* Z8000-Regs:: Register Names
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* Z8000-Addressing:: Addressing Modes
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@end menu
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@node Z8000-Chars
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@subsection Special Characters
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@cindex line comment character, Z8000
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@cindex Z8000 line comment character
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@samp{!} is the line comment character.
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If a @samp{#} appears as the first character of a line then the whole
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line is treated as a comment, but in this case the line could also be
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a logical line number directive (@pxref{Comments}) or a preprocessor
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control command (@pxref{Preprocessing}).
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@cindex line separator, Z8000
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@cindex statement separator, Z8000
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@cindex Z8000 line separator
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You can use @samp{;} instead of a newline to separate statements.
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@node Z8000-Regs
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@subsection Register Names
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@cindex Z8000 registers
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@cindex registers, Z8000
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The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
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to different sized groups of registers by register number, with the
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prefix @samp{r} for 16 bit registers, @samp{rr} for 32 bit registers and
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@samp{rq} for 64 bit registers. You can also refer to the contents of
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the first eight (of the sixteen 16 bit registers) by bytes. They are
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named @samp{rl@var{n}} and @samp{rh@var{n}}.
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@smallexample
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@exdent @emph{byte registers}
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rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
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rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
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@exdent @emph{word registers}
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r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
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@exdent @emph{long word registers}
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rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
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@exdent @emph{quad word registers}
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rq0 rq4 rq8 rq12
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@end smallexample
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@node Z8000-Addressing
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@subsection Addressing Modes
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@cindex addressing modes, Z8000
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@cindex Z800 addressing modes
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@value{AS} understands the following addressing modes for the Z8000:
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@table @code
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@item rl@var{n}
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@itemx rh@var{n}
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@itemx r@var{n}
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@itemx rr@var{n}
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@itemx rq@var{n}
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Register direct: 8bit, 16bit, 32bit, and 64bit registers.
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@item @@r@var{n}
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@itemx @@rr@var{n}
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Indirect register: @@rr@var{n} in segmented mode, @@r@var{n} in unsegmented
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mode.
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@item @var{addr}
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Direct: the 16 bit or 24 bit address (depending on whether the assembler
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is in segmented or unsegmented mode) of the operand is in the instruction.
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@item address(r@var{n})
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Indexed: the 16 or 24 bit address is added to the 16 bit register to produce
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the final address in memory of the operand.
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@item r@var{n}(#@var{imm})
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@itemx rr@var{n}(#@var{imm})
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Base Address: the 16 or 24 bit register is added to the 16 bit sign
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extended immediate displacement to produce the final address in memory
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of the operand.
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@item r@var{n}(r@var{m})
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@itemx rr@var{n}(r@var{m})
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Base Index: the 16 or 24 bit register r@var{n} or rr@var{n} is added to
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the sign extended 16 bit index register r@var{m} to produce the final
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address in memory of the operand.
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@item #@var{xx}
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Immediate data @var{xx}.
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@end table
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@node Z8000 Directives
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@section Assembler Directives for the Z8000
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@cindex Z8000 directives
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@cindex directives, Z8000
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The Z8000 port of @value{AS} includes additional assembler directives,
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for compatibility with other Z8000 assemblers. These do not begin with
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@samp{.} (unlike the ordinary @value{AS} directives).
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@table @code
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@kindex segm
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@item segm
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@kindex .z8001
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@itemx .z8001
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Generate code for the segmented Z8001.
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@kindex unsegm
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@item unsegm
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@kindex .z8002
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@itemx .z8002
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Generate code for the unsegmented Z8002.
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@kindex name
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@item name
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Synonym for @code{.file}
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@kindex global
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@item global
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Synonym for @code{.global}
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@kindex wval
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@item wval
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Synonym for @code{.word}
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@kindex lval
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@item lval
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Synonym for @code{.long}
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@kindex bval
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@item bval
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Synonym for @code{.byte}
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@kindex sval
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@item sval
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Assemble a string. @code{sval} expects one string literal, delimited by
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single quotes. It assembles each byte of the string into consecutive
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addresses. You can use the escape sequence @samp{%@var{xx}} (where
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@var{xx} represents a two-digit hexadecimal number) to represent the
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character whose @sc{ascii} value is @var{xx}. Use this feature to
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describe single quote and other characters that may not appear in string
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literals as themselves. For example, the C statement @w{@samp{char *a =
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"he said \"it's 50% off\"";}} is represented in Z8000 assembly language
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(shown with the assembler output in hex at the left) as
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@iftex
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@begingroup
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@let@nonarrowing=@comment
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@end iftex
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@smallexample
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68652073 sval 'he said %22it%27s 50%25 off%22%00'
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61696420
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22697427
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73203530
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25206F66
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662200
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@end smallexample
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@iftex
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@endgroup
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@end iftex
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@kindex rsect
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@item rsect
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synonym for @code{.section}
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@kindex block
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@item block
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synonym for @code{.space}
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@kindex even
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@item even
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special case of @code{.align}; aligns output to even byte boundary.
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@end table
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@node Z8000 Opcodes
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@section Opcodes
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@cindex Z8000 opcode summary
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@cindex opcode summary, Z8000
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@cindex mnemonics, Z8000
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@cindex instruction summary, Z8000
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For detailed information on the Z8000 machine instruction set, see
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@cite{Z8000 Technical Manual}.
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@ifset SMALL
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@c this table, due to the multi-col faking and hardcoded order, looks silly
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@c except in smallbook. See comments below "@set SMALL" near top of this file.
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The following table summarizes the opcodes and their arguments:
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@iftex
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@begingroup
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@let@nonarrowing=@comment
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@end iftex
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@smallexample
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rs @r{16 bit source register}
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rd @r{16 bit destination register}
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rbs @r{8 bit source register}
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rbd @r{8 bit destination register}
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rrs @r{32 bit source register}
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rrd @r{32 bit destination register}
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rqs @r{64 bit source register}
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rqd @r{64 bit destination register}
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addr @r{16/24 bit address}
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imm @r{immediate data}
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adc rd,rs clrb addr cpsir @@rd,@@rs,rr,cc
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adcb rbd,rbs clrb addr(rd) cpsirb @@rd,@@rs,rr,cc
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add rd,@@rs clrb rbd dab rbd
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add rd,addr com @@rd dbjnz rbd,disp7
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add rd,addr(rs) com addr dec @@rd,imm4m1
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add rd,imm16 com addr(rd) dec addr(rd),imm4m1
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add rd,rs com rd dec addr,imm4m1
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addb rbd,@@rs comb @@rd dec rd,imm4m1
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addb rbd,addr comb addr decb @@rd,imm4m1
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addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
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addb rbd,imm8 comb rbd decb addr,imm4m1
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addb rbd,rbs comflg flags decb rbd,imm4m1
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addl rrd,@@rs cp @@rd,imm16 di i2
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addl rrd,addr cp addr(rd),imm16 div rrd,@@rs
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addl rrd,addr(rs) cp addr,imm16 div rrd,addr
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addl rrd,imm32 cp rd,@@rs div rrd,addr(rs)
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addl rrd,rrs cp rd,addr div rrd,imm16
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and rd,@@rs cp rd,addr(rs) div rrd,rs
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and rd,addr cp rd,imm16 divl rqd,@@rs
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and rd,addr(rs) cp rd,rs divl rqd,addr
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and rd,imm16 cpb @@rd,imm8 divl rqd,addr(rs)
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and rd,rs cpb addr(rd),imm8 divl rqd,imm32
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andb rbd,@@rs cpb addr,imm8 divl rqd,rrs
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andb rbd,addr cpb rbd,@@rs djnz rd,disp7
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andb rbd,addr(rs) cpb rbd,addr ei i2
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andb rbd,imm8 cpb rbd,addr(rs) ex rd,@@rs
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andb rbd,rbs cpb rbd,imm8 ex rd,addr
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bit @@rd,imm4 cpb rbd,rbs ex rd,addr(rs)
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bit addr(rd),imm4 cpd rd,@@rs,rr,cc ex rd,rs
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bit addr,imm4 cpdb rbd,@@rs,rr,cc exb rbd,@@rs
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bit rd,imm4 cpdr rd,@@rs,rr,cc exb rbd,addr
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bit rd,rs cpdrb rbd,@@rs,rr,cc exb rbd,addr(rs)
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bitb @@rd,imm4 cpi rd,@@rs,rr,cc exb rbd,rbs
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bitb addr(rd),imm4 cpib rbd,@@rs,rr,cc ext0e imm8
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bitb addr,imm4 cpir rd,@@rs,rr,cc ext0f imm8
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bitb rbd,imm4 cpirb rbd,@@rs,rr,cc ext8e imm8
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bitb rbd,rs cpl rrd,@@rs ext8f imm8
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bpt cpl rrd,addr exts rrd
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call @@rd cpl rrd,addr(rs) extsb rd
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call addr cpl rrd,imm32 extsl rqd
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call addr(rd) cpl rrd,rrs halt
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calr disp12 cpsd @@rd,@@rs,rr,cc in rd,@@rs
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clr @@rd cpsdb @@rd,@@rs,rr,cc in rd,imm16
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clr addr cpsdr @@rd,@@rs,rr,cc inb rbd,@@rs
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clr addr(rd) cpsdrb @@rd,@@rs,rr,cc inb rbd,imm16
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clr rd cpsi @@rd,@@rs,rr,cc inc @@rd,imm4m1
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clrb @@rd cpsib @@rd,@@rs,rr,cc inc addr(rd),imm4m1
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inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
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inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
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incb @@rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
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incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@@rs
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incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
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incb rbd,imm4m1 ldd @@rs,@@rd,rr multl rqd,addr(rs)
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ind @@rd,@@rs,ra lddb @@rs,@@rd,rr multl rqd,imm32
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indb @@rd,@@rs,rba lddr @@rs,@@rd,rr multl rqd,rrs
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inib @@rd,@@rs,ra lddrb @@rs,@@rd,rr neg @@rd
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inibr @@rd,@@rs,ra ldi @@rd,@@rs,rr neg addr
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iret ldib @@rd,@@rs,rr neg addr(rd)
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jp cc,@@rd ldir @@rd,@@rs,rr neg rd
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jp cc,addr ldirb @@rd,@@rs,rr negb @@rd
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jp cc,addr(rd) ldk rd,imm4 negb addr
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jr cc,disp8 ldl @@rd,rrs negb addr(rd)
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ld @@rd,imm16 ldl addr(rd),rrs negb rbd
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ld @@rd,rs ldl addr,rrs nop
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ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@@rs
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ld addr(rd),rs ldl rd(rx),rrs or rd,addr
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ld addr,imm16 ldl rrd,@@rs or rd,addr(rs)
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ld addr,rs ldl rrd,addr or rd,imm16
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ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
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ld rd(rx),rs ldl rrd,imm32 orb rbd,@@rs
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ld rd,@@rs ldl rrd,rrs orb rbd,addr
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ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
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ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
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ld rd,imm16 ldm @@rd,rs,n orb rbd,rbs
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ld rd,rs ldm addr(rd),rs,n out @@rd,rs
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ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
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ld rd,rs(rx) ldm rd,@@rs,n outb @@rd,rbs
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lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
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lda rd,addr(rs) ldm rd,addr,n outd @@rd,@@rs,ra
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lda rd,rs(imm16) ldps @@rs outdb @@rd,@@rs,rba
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lda rd,rs(rx) ldps addr outib @@rd,@@rs,ra
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ldar rd,disp16 ldps addr(rs) outibr @@rd,@@rs,ra
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ldb @@rd,imm8 ldr disp16,rs pop @@rd,@@rs
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ldb @@rd,rbs ldr rd,disp16 pop addr(rd),@@rs
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ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@@rs
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ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@@rs
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ldb addr,imm8 ldrl disp16,rrs popl @@rd,@@rs
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ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@@rs
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ldb rbd,@@rs mbit popl addr,@@rs
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ldb rbd,addr mreq rd popl rrd,@@rs
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ldb rbd,addr(rs) mres push @@rd,@@rs
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ldb rbd,imm8 mset push @@rd,addr
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ldb rbd,rbs mult rrd,@@rs push @@rd,addr(rs)
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ldb rbd,rs(imm16) mult rrd,addr push @@rd,imm16
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push @@rd,rs set addr,imm4 subl rrd,imm32
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pushl @@rd,@@rs set rd,imm4 subl rrd,rrs
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pushl @@rd,addr set rd,rs tcc cc,rd
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pushl @@rd,addr(rs) setb @@rd,imm4 tccb cc,rbd
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pushl @@rd,rrs setb addr(rd),imm4 test @@rd
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res @@rd,imm4 setb addr,imm4 test addr
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res addr(rd),imm4 setb rbd,imm4 test addr(rd)
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res addr,imm4 setb rbd,rs test rd
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res rd,imm4 setflg imm4 testb @@rd
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res rd,rs sinb rbd,imm16 testb addr
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resb @@rd,imm4 sinb rd,imm16 testb addr(rd)
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resb addr(rd),imm4 sind @@rd,@@rs,ra testb rbd
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resb addr,imm4 sindb @@rd,@@rs,rba testl @@rd
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resb rbd,imm4 sinib @@rd,@@rs,ra testl addr
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resb rbd,rs sinibr @@rd,@@rs,ra testl addr(rd)
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resflg imm4 sla rd,imm8 testl rrd
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ret cc slab rbd,imm8 trdb @@rd,@@rs,rba
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rl rd,imm1or2 slal rrd,imm8 trdrb @@rd,@@rs,rba
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rlb rbd,imm1or2 sll rd,imm8 trib @@rd,@@rs,rbr
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rlc rd,imm1or2 sllb rbd,imm8 trirb @@rd,@@rs,rbr
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rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @@ra,@@rb,rbr
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rldb rbb,rba sout imm16,rs trtib @@ra,@@rb,rr
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rr rd,imm1or2 soutb imm16,rbs trtirb @@ra,@@rb,rbr
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rrb rbd,imm1or2 soutd @@rd,@@rs,ra trtrb @@ra,@@rb,rbr
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rrc rd,imm1or2 soutdb @@rd,@@rs,rba tset @@rd
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rrcb rbd,imm1or2 soutib @@rd,@@rs,ra tset addr
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rrdb rbb,rba soutibr @@rd,@@rs,ra tset addr(rd)
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rsvd36 sra rd,imm8 tset rd
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rsvd38 srab rbd,imm8 tsetb @@rd
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rsvd78 sral rrd,imm8 tsetb addr
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rsvd7e srl rd,imm8 tsetb addr(rd)
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rsvd9d srlb rbd,imm8 tsetb rbd
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rsvd9f srll rrd,imm8 xor rd,@@rs
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rsvdb9 sub rd,@@rs xor rd,addr
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rsvdbf sub rd,addr xor rd,addr(rs)
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sbc rd,rs sub rd,addr(rs) xor rd,imm16
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sbcb rbd,rbs sub rd,imm16 xor rd,rs
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sc imm8 sub rd,rs xorb rbd,@@rs
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sda rd,rs subb rbd,@@rs xorb rbd,addr
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sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
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sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
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sdl rd,rs subb rbd,imm8 xorb rbd,rbs
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sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
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sdll rrd,rs subl rrd,@@rs
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set @@rd,imm4 subl rrd,addr
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set addr(rd),imm4 subl rrd,addr(rs)
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@end smallexample
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@iftex
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@endgroup
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@end iftex
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@end ifset
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