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https://sourceware.org/git/binutils-gdb.git
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9335d9f823
Now that ChangeLog entries are no longer used for sim patches, this commit renames all relevant sim ChangeLog to ChangeLog-2021, similar to what we would do in the context of the "Start of New Year" procedure. The purpose of this change is to avoid people merging ChangeLog entries by mistake when applying existing commits that they are currently working on. Also throw in a .gitignore entry to keep people from adding new ChangeLog files anywhere in the sim tree.
141 lines
4.0 KiB
Plaintext
141 lines
4.0 KiB
Plaintext
2021-07-01 Mike Frysinger <vapier@gentoo.org>
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* hw-trap.ms: Run sim with --environment virtual.
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* trap.cgs: Likewise.
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2021-04-08 Mike Frysinger <vapier@gentoo.org>
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* allinsn.exp (arch): Delete.
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* misc.exp: Likewise.
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2021-02-13 Mike Frysinger <vapier@gentoo.org>
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* allinsn.exp, misc.exp: Define arch.
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2021-01-15 Mike Frysinger <vapier@gentoo.org>
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* exit47.ms: New testcase from ../../m32r-elf/.
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1999-04-21 Doug Evans <devans@casey.cygnus.com>
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* nop.cgs: Add missing nop insn.
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1999-01-05 Doug Evans <devans@casey.cygnus.com>
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* allinsn.exp: Set all_machs.
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* misc.exp: Likewise.
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1998-12-14 Doug Evans <devans@casey.cygnus.com>
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* hello.ms: Add trailing \n to expected output.
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* hw-trap.ms: Ditto.
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* trap.cgs: Properly align trap2_handler.
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* uread16.ms: New testcase.
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* uread32.ms: New testcase.
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* uwrite16.ms: New testcase.
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* uwrite32.ms: New testcase.
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Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com>
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* testutils.inc (test_h_gr): Use mvaddr_h_gr.
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* rte.cgs: Test bbpc,bbpsw.
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* trap.cgs: Test bbpc,bbpsw.
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Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com>
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* hw-trap.ms: New testcase.
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Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com>
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* addx.cgs: Add another test.
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* jmp.cgs: Add another test.
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Mon Jun 8 16:08:27 1998 Doug Evans <devans@canuck.cygnus.com>
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* trap.cgs: Test trap 2.
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Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com>
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* addx.cgs: Test (-1)+(-1)+1.
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Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com>
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* mv[ft]achi.cgs: Fix expected result
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(sign extension of top 8 bits).
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Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
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* unlock.cgs: Fixed test.
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* mvfc.cgs: Fixed test.
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* remu.cgs: Fixed test.
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* bnc24.cgs: Test long BNC instruction.
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* bnc8.cgs: Test short BNC instruction.
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* ld-plus.cgs: Test LD instruction.
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* macwhi.cgs: Test MACWHI instruction.
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* macwlo.cgs: Test MACWLO instruction.
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* mulwhi.cgs: Test MULWHI instruction.
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* mulwlo.cgs: Test MULWLO instruction.
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* mvfachi.cgs: Test MVFACHI instruction.
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* mvfaclo.cgs: Test MVFACLO instruction.
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* mvtaclo.cgs: Test MVTACLO instruction.
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* addv.cgs: Test ADDV instruction.
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* addv3.cgs: Test ADDV3 instruction.
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* addx.cgs: Test ADDX instruction.
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* lock.cgs: Test LOCK instruction.
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* neg.cgs: Test NEG instruction.
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* not.cgs: Test NOT instruction.
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* unlock.cgs: Test UNLOCK instruction.
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Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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* testutils.inc (mvaddr_h_gr): new macro to load an
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address into a general register.
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* or3.cgs: Test OR3 instruction.
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* rach.cgs: Test RACH instruction.
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* rem.cgs: Test REM instruction.
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* sub.cgs: Test SUB instruction.
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* mv.cgs: Test MV instruction.
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* mul.cgs: Test MUL instruction.
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* bl24.cgs: Test long BL instruction.
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* bl8.cgs: Test short BL instruction.
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* blez.cgs: Test BLEZ instruction.
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* bltz.cgs: Test BLTZ instruction.
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* bne.cgs: Test BNE instruction.
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* bnez.cgs: Test BNEZ instruction.
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* bra24.cgs: Test long BRA instruction.
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* bra8.cgs: Test short BRA instruction.
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* jl.cgs: Test JL instruction.
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* or.cgs: Test OR instruction.
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* jmp.cgs: Test JMP instruction.
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* and.cgs: Test AND instruction.
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* and3.cgs: Test AND3 instruction.
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* beq.cgs: Test BEQ instruction.
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* beqz.cgs: Test BEQZ instruction.
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* bgez.cgs: Test BGEZ instruction.
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* bgtz.cgs: Test BGTZ instruction.
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* cmp.cgs: Test CMP instruction.
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* cmpi.cgs: Test CMPI instruction.
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* cmpu.cgs: Test CMPU instruction.
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* cmpui.cgs: Test CMPUI instruction.
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* div.cgs: Test DIV instruction.
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* divu.cgs: Test DIVU instruction.
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* cmpeq.cgs: Test CMPEQ instruction.
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* sll.cgs: Test SLL instruction.
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* sll3.cgs: Test SLL3 instruction.
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* slli.cgs: Test SLLI instruction.
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* sra.cgs: Test SRA instruction.
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* sra3.cgs: Test SRA3 instruction.
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* srai.cgs: Test SRAI instruction.
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* srl.cgs: Test SRL instruction.
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* srl3.cgs: Test SRL3 instruction.
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* srli.cgs: Test SRLI instruction.
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* xor3.cgs: Test XOR3 instruction.
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* xor.cgs: Test XOR instruction.
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Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
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* *: m32r dejagnu simulator testsuite.
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