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8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
629 lines
18 KiB
C
629 lines
18 KiB
C
/* CRIS v32 simulator support code
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Copyright (C) 2004-2013 Free Software Foundation, Inc.
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Contributed by Axis Communications.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* The infrastructure is based on that of i960.c. */
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#define WANT_CPU_CRISV32F
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#define SPECIFIC_U_EXEC_FN
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#define SPECIFIC_U_SKIP4_FN
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#define SPECIFIC_U_CONST16_FN
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#define SPECIFIC_U_CONST32_FN
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#define SPECIFIC_U_MEM_FN
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#define SPECIFIC_U_MOVEM_FN
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#define BASENUM 32
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#define CRIS_TLS_REGISTER 2
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#include "cris-tmpl.c"
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#if WITH_PROFILE_MODEL_P
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/* Re-use the bit position for the BZ register, since there are no stall
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cycles for reading or writing it. */
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#define CRIS_BZ_REGNO 16
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#define CRIS_MODF_JUMP_MASK (1 << CRIS_BZ_REGNO)
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/* Likewise for the WZ register, marking memory writes. */
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#define CRIS_WZ_REGNO 20
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#define CRIS_MODF_MEM_WRITE_MASK (1 << CRIS_WZ_REGNO)
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#define CRIS_MOF_REGNO (16 + 7)
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#define CRIS_ALWAYS_CONDITION 14
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/* This macro must only be used in context where there's only one
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dynamic cause for a penalty, except in the u-exec unit. */
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#define PENALIZE1(CNT) \
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do \
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{ \
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CPU_CRIS_MISC_PROFILE (current_cpu)->CNT++; \
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model_data->prev_prev_prev_modf_regs \
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= model_data->prev_prev_modf_regs; \
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model_data->prev_prev_modf_regs \
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= model_data->prev_modf_regs; \
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model_data->prev_modf_regs = 0; \
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model_data->prev_prev_prev_movem_dest_regs \
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= model_data->prev_prev_movem_dest_regs; \
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model_data->prev_prev_movem_dest_regs \
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= model_data->prev_movem_dest_regs; \
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model_data->prev_movem_dest_regs = 0; \
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} \
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while (0)
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/* Model function for u-skip4 unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_skip4)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED)
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{
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU (h_pc) += 4;
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return 0;
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}
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/* Model function for u-exec unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_exec)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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INT destreg_in,
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INT srcreg,
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INT destreg_out)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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UINT modf_regs
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= ((destreg_out == -1 ? 0 : (1 << destreg_out))
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| model_data->modf_regs);
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if (srcreg != -1)
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{
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if (model_data->prev_movem_dest_regs & (1 << srcreg))
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{
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PENALIZE1 (movemdst_stall_count);
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PENALIZE1 (movemdst_stall_count);
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PENALIZE1 (movemdst_stall_count);
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}
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else if (model_data->prev_prev_movem_dest_regs & (1 << srcreg))
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{
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PENALIZE1 (movemdst_stall_count);
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PENALIZE1 (movemdst_stall_count);
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}
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else if (model_data->prev_prev_prev_movem_dest_regs & (1 << srcreg))
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PENALIZE1 (movemdst_stall_count);
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}
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if (destreg_in != -1)
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{
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if (model_data->prev_movem_dest_regs & (1 << destreg_in))
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{
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PENALIZE1 (movemdst_stall_count);
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PENALIZE1 (movemdst_stall_count);
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PENALIZE1 (movemdst_stall_count);
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}
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else if (model_data->prev_prev_movem_dest_regs & (1 << destreg_in))
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{
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PENALIZE1 (movemdst_stall_count);
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PENALIZE1 (movemdst_stall_count);
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}
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else if (model_data->prev_prev_prev_movem_dest_regs & (1 << destreg_in))
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PENALIZE1 (movemdst_stall_count);
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}
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model_data->prev_prev_prev_modf_regs
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= model_data->prev_prev_modf_regs;
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model_data->prev_prev_modf_regs = model_data->prev_modf_regs;
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model_data->prev_modf_regs = modf_regs;
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model_data->modf_regs = 0;
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model_data->prev_prev_prev_movem_dest_regs
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= model_data->prev_prev_movem_dest_regs;
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model_data->prev_prev_movem_dest_regs = model_data->prev_movem_dest_regs;
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model_data->prev_movem_dest_regs = model_data->movem_dest_regs;
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model_data->movem_dest_regs = 0;
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU (h_pc) += 2;
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return 1;
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}
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/* Special case used when the destination is a special register. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_exec_to_sr)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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INT srcreg,
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INT specreg)
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{
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int specdest;
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if (specreg != -1)
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specdest = specreg + 16;
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else
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abort ();
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return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_exec))
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(current_cpu, NULL, 0, 0, -1, srcreg,
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/* The positions for constant-zero registers BZ and WZ are recycled
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for jump and memory-write markers. We must take precautions
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here not to add false markers for them. It might be that the
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hardware inserts stall cycles for instructions that actually try
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and write those registers, but we'll burn that bridge when we
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get to it; we'd have to find other free bits or make new
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model_data variables. However, it's doubtful that there will
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ever be a need to be cycle-correct for useless code, at least in
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this particular simulator, mainly used for GCC testing. */
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specdest == CRIS_BZ_REGNO || specdest == CRIS_WZ_REGNO
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? -1 : specdest);
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}
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/* Special case for movem. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_exec_movem)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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INT srcreg,
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INT destreg_out)
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{
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return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_exec))
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(current_cpu, NULL, 0, 0, -1, srcreg, destreg_out);
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}
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/* Model function for u-const16 unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_const16)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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/* If the previous insn was a jump of some sort and this insn
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straddles a cache-line, there's a one-cycle penalty.
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FIXME: Test-cases for normal const16 and others, like branch. */
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if ((model_data->prev_modf_regs & CRIS_MODF_JUMP_MASK)
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&& (CPU (h_pc) & 0x1e) == 0x1e)
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PENALIZE1 (jumptarget_stall_count);
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU (h_pc) += 2;
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return 0;
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}
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/* Model function for u-const32 unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_const32)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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/* If the previous insn was a jump of some sort and this insn
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straddles a cache-line, there's a one-cycle penalty. */
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if ((model_data->prev_modf_regs & CRIS_MODF_JUMP_MASK)
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&& (CPU (h_pc) & 0x1e) == 0x1c)
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PENALIZE1 (jumptarget_stall_count);
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/* Handle PC not being updated with pbb. FIXME: What if not pbb? */
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CPU (h_pc) += 4;
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return 0;
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}
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/* Model function for u-mem unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_mem)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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INT srcreg)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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if (srcreg == -1)
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abort ();
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/* If srcreg references a register modified in the previous cycle
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through other than autoincrement, then there's a penalty: one
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cycle. */
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if (model_data->prev_modf_regs & (1 << srcreg))
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PENALIZE1 (memsrc_stall_count);
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return 0;
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}
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/* Model function for u-mem-r unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_mem_r)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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/* There's a two-cycle penalty for read after a memory write in any of
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the two previous cycles, known as a cache read-after-write hazard.
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This model function (the model_data member access) depends on being
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executed before the u-exec unit. */
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if ((model_data->prev_modf_regs & CRIS_MODF_MEM_WRITE_MASK)
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|| (model_data->prev_prev_modf_regs & CRIS_MODF_MEM_WRITE_MASK))
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{
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PENALIZE1 (memraw_stall_count);
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PENALIZE1 (memraw_stall_count);
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}
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return 0;
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}
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/* Model function for u-mem-w unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_mem_w)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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/* Mark that memory has been written. This model function (the
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model_data member access) depends on being executed after the
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u-exec unit. */
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model_data->prev_modf_regs |= CRIS_MODF_MEM_WRITE_MASK;
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return 0;
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}
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/* Model function for u-movem-rtom unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_movem_rtom)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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/* Deliberate order. */
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INT addrreg, INT limreg)
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{
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USI addr;
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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if (limreg == -1 || addrreg == -1)
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abort ();
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addr = GET_H_GR (addrreg);
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/* The movem-to-memory instruction must not move a register modified
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in one of the previous two cycles. Enforce by adding penalty
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cycles. */
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if (model_data->prev_modf_regs & ((1 << (limreg + 1)) - 1))
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{
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PENALIZE1 (movemsrc_stall_count);
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PENALIZE1 (movemsrc_stall_count);
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}
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else if (model_data->prev_prev_modf_regs & ((1 << (limreg + 1)) - 1))
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PENALIZE1 (movemsrc_stall_count);
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/* One-cycle penalty for each cache-line straddled. Use the
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documented expressions. Unfortunately no penalty cycles are
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eliminated by any penalty cycles above. We file these numbers
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separately, since they aren't schedulable for all cases. */
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if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5))
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;
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else if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5) - 1)
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PENALIZE1 (movemaddr_stall_count);
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else if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5) - 2)
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{
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PENALIZE1 (movemaddr_stall_count);
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PENALIZE1 (movemaddr_stall_count);
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}
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else
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abort ();
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return 0;
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}
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/* Model function for u-movem-mtor unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_movem_mtor)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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/* Deliberate order. */
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INT addrreg, INT limreg)
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{
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USI addr;
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int nregs = limreg + 1;
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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if (limreg == -1 || addrreg == -1)
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abort ();
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addr = GET_H_GR (addrreg);
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/* One-cycle penalty for each cache-line straddled. Use the
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documented expressions. One cycle is the norm; more cycles are
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counted as penalties. Unfortunately no penalty cycles here
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eliminate penalty cycles indicated in ->movem_dest_regs. */
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if ((addr >> 5) == (((addr + 4 * nregs) - 1) >> 5) - 1)
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PENALIZE1 (movemaddr_stall_count);
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else if ((addr >> 5) == (((addr + 4 * nregs) - 1) >> 5) - 2)
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{
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PENALIZE1 (movemaddr_stall_count);
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PENALIZE1 (movemaddr_stall_count);
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}
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model_data->modf_regs |= ((1 << nregs) - 1);
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model_data->movem_dest_regs |= ((1 << nregs) - 1);
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return 0;
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}
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/* Model function for u-branch unit.
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FIXME: newpc and cc are always wrong. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,_u_branch)) (SIM_CPU *current_cpu,
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const IDESC *idesc,
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int unit_num, int referenced)
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{
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CRIS_MISC_PROFILE *profp = CPU_CRIS_MISC_PROFILE (current_cpu);
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USI pc = profp->old_pc;
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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int taken = profp->branch_taken;
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int branch_index = (pc & (N_CRISV32_BRANCH_PREDICTORS - 1)) >> 1;
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int pred_taken = (profp->branch_predictors[branch_index] & 2) != 0;
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if (taken != pred_taken)
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{
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PENALIZE1 (branch_stall_count);
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PENALIZE1 (branch_stall_count);
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}
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if (taken)
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{
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if (profp->branch_predictors[branch_index] < 3)
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profp->branch_predictors[branch_index]++;
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return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump))
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(current_cpu, idesc, unit_num, referenced, -1);
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}
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if (profp->branch_predictors[branch_index] != 0)
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profp->branch_predictors[branch_index]--;
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return 0;
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}
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/* Model function for u-jump-r unit. */
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int
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MY (XCONCAT3 (f_model_crisv,BASENUM,
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_u_jump_r)) (SIM_CPU *current_cpu,
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const IDESC *idesc ATTRIBUTE_UNUSED,
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int unit_num ATTRIBUTE_UNUSED,
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int referenced ATTRIBUTE_UNUSED,
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int regno)
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{
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MODEL_CRISV32_DATA *model_data
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= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
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if (regno == -1)
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abort ();
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/* For jump-to-register, the register must not have been modified the
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last two cycles. Penalty: two cycles from the modifying insn. */
|
|
if ((1 << regno) & model_data->prev_modf_regs)
|
|
{
|
|
PENALIZE1 (jumpsrc_stall_count);
|
|
PENALIZE1 (jumpsrc_stall_count);
|
|
}
|
|
else if ((1 << regno) & model_data->prev_prev_modf_regs)
|
|
PENALIZE1 (jumpsrc_stall_count);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Model function for u-jump-sr unit. */
|
|
|
|
int
|
|
MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump_sr)) (SIM_CPU *current_cpu,
|
|
const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
int sr_regno)
|
|
{
|
|
int regno;
|
|
|
|
MODEL_CRISV32_DATA *model_data
|
|
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
|
|
|
if (sr_regno == -1)
|
|
abort ();
|
|
|
|
regno = sr_regno + 16;
|
|
|
|
/* For jump-to-register, the register must not have been modified the
|
|
last two cycles. Penalty: two cycles from the modifying insn. */
|
|
if ((1 << regno) & model_data->prev_modf_regs)
|
|
{
|
|
PENALIZE1 (jumpsrc_stall_count);
|
|
PENALIZE1 (jumpsrc_stall_count);
|
|
}
|
|
else if ((1 << regno) & model_data->prev_prev_modf_regs)
|
|
PENALIZE1 (jumpsrc_stall_count);
|
|
|
|
return
|
|
MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump)) (current_cpu, idesc,
|
|
unit_num, referenced, -1);
|
|
}
|
|
|
|
/* Model function for u-jump unit. */
|
|
|
|
int
|
|
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
|
_u_jump)) (SIM_CPU *current_cpu,
|
|
const IDESC *idesc ATTRIBUTE_UNUSED,
|
|
int unit_num ATTRIBUTE_UNUSED,
|
|
int referenced ATTRIBUTE_UNUSED,
|
|
int out_sr_regno)
|
|
{
|
|
MODEL_CRISV32_DATA *model_data
|
|
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
|
|
|
/* Mark that we made a jump. */
|
|
model_data->modf_regs
|
|
|= (CRIS_MODF_JUMP_MASK
|
|
| (out_sr_regno == -1 || out_sr_regno == CRIS_BZ_REGNO
|
|
? 0 : (1 << (out_sr_regno + 16))));
|
|
return 0;
|
|
}
|
|
|
|
/* Model function for u-multiply unit. */
|
|
|
|
int
|
|
MY (XCONCAT3 (f_model_crisv,BASENUM,
|
|
_u_multiply)) (SIM_CPU *current_cpu,
|
|
const IDESC *idesc ATTRIBUTE_UNUSED,
|
|
int unit_num ATTRIBUTE_UNUSED,
|
|
int referenced ATTRIBUTE_UNUSED,
|
|
int srcreg, int destreg)
|
|
{
|
|
MODEL_CRISV32_DATA *model_data
|
|
= (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
|
|
|
|
/* Sanity-check for cases that should never happen. */
|
|
if (srcreg == -1 || destreg == -1)
|
|
abort ();
|
|
|
|
/* This takes extra cycles when one of the inputs has been modified
|
|
through other than autoincrement in the previous cycle. Penalty:
|
|
one cycle. */
|
|
if (((1 << srcreg) | (1 << destreg)) & model_data->prev_modf_regs)
|
|
PENALIZE1 (mulsrc_stall_count);
|
|
|
|
/* We modified the multiplication destination (marked in u-exec) and
|
|
the MOF register. */
|
|
model_data->modf_regs |= (1 << CRIS_MOF_REGNO);
|
|
return 0;
|
|
}
|
|
|
|
#endif /* WITH_PROFILE_MODEL_P */
|
|
|
|
int
|
|
MY (deliver_interrupt) (SIM_CPU *current_cpu,
|
|
enum cris_interrupt_type type,
|
|
unsigned int vec)
|
|
{
|
|
unsigned32 old_ccs, shifted_ccs, new_ccs;
|
|
unsigned char entryaddr_le[4];
|
|
int was_user;
|
|
SIM_DESC sd = CPU_STATE (current_cpu);
|
|
unsigned32 entryaddr;
|
|
|
|
/* We haven't implemented other interrupt-types yet. */
|
|
if (type != CRIS_INT_INT)
|
|
abort ();
|
|
|
|
/* We're called outside of branch delay slots etc, so we don't check
|
|
for that. */
|
|
if (!GET_H_IBIT_V32 ())
|
|
return 0;
|
|
|
|
old_ccs = GET_H_SR_V32 (H_SR_CCS);
|
|
shifted_ccs = (old_ccs << 10) & ((1 << 30) - 1);
|
|
|
|
/* The M bit is handled by code below and the M bit setter function, but
|
|
we need to preserve the Q bit. */
|
|
new_ccs = shifted_ccs | (old_ccs & (unsigned32) 0x80000000UL);
|
|
was_user = GET_H_UBIT_V32 ();
|
|
|
|
/* We need to force kernel mode since the setter method doesn't allow
|
|
it. Then we can use setter methods at will, since they then
|
|
recognize that we're in kernel mode. */
|
|
CPU (h_ubit_v32) = 0;
|
|
|
|
SET_H_SR (H_SR_CCS, new_ccs);
|
|
|
|
if (was_user)
|
|
{
|
|
/* These methods require that user mode is unset. */
|
|
SET_H_SR (H_SR_USP, GET_H_GR (H_GR_SP));
|
|
SET_H_GR (H_GR_SP, GET_H_KERNEL_SP ());
|
|
}
|
|
|
|
/* ERP setting is simplified by not taking interrupts in delay-slots
|
|
or when halting. */
|
|
/* For all other exceptions than guru and NMI, store the return
|
|
address in ERP and set EXS and EXD here. */
|
|
SET_H_SR (H_SR_ERP, GET_H_PC ());
|
|
|
|
/* Simplified by not having exception types (fault indications). */
|
|
SET_H_SR_V32 (H_SR_EXS, (vec * 256));
|
|
SET_H_SR_V32 (H_SR_EDA, 0);
|
|
|
|
if (sim_core_read_buffer (sd,
|
|
current_cpu,
|
|
read_map, entryaddr_le,
|
|
GET_H_SR (H_SR_EBP) + vec * 4, 4) == 0)
|
|
{
|
|
/* Nothing to do actually; either abort or send a signal. */
|
|
sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4,
|
|
GET_H_SR (H_SR_EBP) + vec * 4,
|
|
read_transfer, sim_core_unmapped_signal);
|
|
return 0;
|
|
}
|
|
|
|
entryaddr = bfd_getl32 (entryaddr_le);
|
|
SET_H_PC (entryaddr);
|
|
|
|
return 1;
|
|
}
|