mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-21 01:12:32 +08:00
…
|
||
---|---|---|
.. | ||
ChangeLog-2021 | ||
example-synacor-sim.h | ||
interp.c | ||
local.mk | ||
README | ||
README.arch-spec | ||
sim-main.c | ||
sim-main.h |
= OVERVIEW = The Synacor Challenge is a fun programming exercise with a number of puzzles built into it. You can find more details about it here: https://challenge.synacor.com/ The first puzzle is writing an interpreter for their custom ISA. This is a simulator for that custom CPU. The CPU is quite basic: it's 16-bit with only 8 registers and a limited set of instructions. This means the port will never grow new features. See README.arch-spec for more details. Implementing it here ends up being quite useful: it acts as a simple constrained "real world" example for people who want to implement a new simulator for their own architecture. We demonstrate all the basic fundamentals (registers, memory, branches, and tracing) that all ports should have.