Christoph Müllner 704b30cbb2 RISC-V: Zvkh[a,b]: Remove individual instruction class ... Currently we have three instruction classes defined for Zvkh[a,b]: - INSN_CLASS_ZVKNHA - INSN_CLASS_ZVKNHB - INSN_CLASS_ZVKNHA_OR_ZVKNHB The encodings of all instructions in Zvknh[a,b] are identical. Therefore, we don't need the individual instruction classes and can remove them. This patch also adds the missing support of the combined instruction class in riscv_multi_subset_supports_ext(). Fixes: 62edb233ef ("RISC-V: Add support for the Zvknh[a,b] ISA extensions") Reported-By: Nelson Chu <nelson@rivosinc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>		2023-07-03 18:17:59 +08:00
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aarch64.h
alpha.h
arc-attrs.h
arc-func.h
arc.h
arm.h
avr.h
bfin.h
cgen.h
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h
cris.h
crx.h
csky.h
d10v.h
d30v.h
dlx.h
ft32.h
h8300.h
hppa.h
i386.h
ia64.h
loongarch.h	LoongArch: gas: Add LVZ and LBT instructions support	2023-06-30 17:32:28 +08:00
m68hc11.h
m68k.h
metag.h
mips.h	Add MIPS Allegrex CPU as a MIPS2-based CPU	2023-06-15 04:45:03 +01:00
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h
nfp.h
nios2.h
nios2r1.h
nios2r2.h
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h
pru.h
pyr.h
riscv-opc.h	RISC-V: Add support for the Zvksh ISA extension	2023-07-01 07:28:40 -06:00
riscv.h	RISC-V: Zvkh[a,b]: Remove individual instruction class	2023-07-03 18:17:59 +08:00
rl78.h
rx.h
s12z.h
s390.h
score-datadep.h
score-inst.h
sparc.h
spu-insns.h
spu.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h
tic6x.h
tic30.h
tic54x.h
tilegx.h
tilepro.h
v850.h
vax.h
visium.h
wasm.h
xgate.h