Peter Gavin 702d582e2c sim: testsuite: add testsuite for or1k sim ... This is the testsuite for the or1k sim, it tests running many of the basic architecture instructions on the openrisc sim. sim/testsuite/sim/or1k/ChangeLog: 2017-12-12 Peter Gavin <pgavin@gmail.com> Stafford Horne <shorne@gmail.com> * add.S: New file. * alltests.exp: New file. * and.S: New file. * basic.S: New file. * div.S: New file. * ext.S: New file. * find.S: New file. * flag.S: New file. * fpu.S: New file. * jump.S: New file. * load.S: New file. * mac.S: New file. * mfspr.S: New file. * mul.S: New file. * or.S: New file. * or1k-asm-test-env.h: New file. * or1k-asm-test-helpers.h: New file. * or1k-asm-test.h: New file. * or1k-asm.h: New file. * or1k-test.ld: New file. * ror.S: New file. * shift.S: New file. * spr-defs.h: New file. * sub.S: New file. * xor.S: New file. sim/testsuite/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure: Regenerated.		2017-12-12 23:49:57 +09:00
..
aarch64
arm	[SIM, ARM] Fix build failure	2017-09-21 09:02:25 +01:00
avr
bfin
common	sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])	2017-12-12 23:43:02 +09:00
cr16
cris
d10v
erc32
frv
ft32	FT32: support for FT32B processor - part 2/2	2017-11-01 18:36:51 -07:00
h8300
igen
iq2000
lm32
m32c
m32r
m68hc11
mcore
microblaze
mips
mn10300
moxie
msp430
or1k	sim: or1k: add autoconf generated files	2017-12-12 23:46:53 +09:00
ppc
rl78
rx
sh
sh64
testsuite	sim: testsuite: add testsuite for or1k sim	2017-12-12 23:49:57 +09:00
v850
.gitignore
ChangeLog	sim: or1k: add autoconf generated files	2017-12-12 23:46:53 +09:00
configure	sim: or1k: add autoconf generated files	2017-12-12 23:46:53 +09:00
configure.ac
configure.tgt	sim: or1k: add or1k target to sim	2017-12-12 23:44:14 +09:00
MAINTAINERS	Add myself as ft32 maintainer for sim.	2017-10-12 18:12:42 -07:00
Makefile.in
README-HACKING