mirror of
https://sourceware.org/git/binutils-gdb.git
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213516ef31
This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
175 lines
7.6 KiB
XML
175 lines
7.6 KiB
XML
<?xml version="1.0"?>
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<!-- Copyright (C) 2009-2023 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.aarch64.fpu">
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<vector id="v2d" type="ieee_double" count="2"/>
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<vector id="v2u" type="uint64" count="2"/>
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<vector id="v2i" type="int64" count="2"/>
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<vector id="v4f" type="ieee_single" count="4"/>
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<vector id="v4u" type="uint32" count="4"/>
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<vector id="v4i" type="int32" count="4"/>
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<vector id="v8f" type="ieee_half" count="8"/>
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<vector id="v8u" type="uint16" count="8"/>
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<vector id="v8i" type="int16" count="8"/>
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<vector id="v8bf16" type="bfloat16" count="8"/>
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<vector id="v16u" type="uint8" count="16"/>
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<vector id="v16i" type="int8" count="16"/>
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<vector id="v1u" type="uint128" count="1"/>
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<vector id="v1i" type="int128" count="1"/>
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<union id="vnd">
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<field name="f" type="v2d"/>
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<field name="u" type="v2u"/>
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<field name="s" type="v2i"/>
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</union>
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<union id="vns">
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<field name="f" type="v4f"/>
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<field name="u" type="v4u"/>
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<field name="s" type="v4i"/>
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</union>
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<union id="vnh">
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<field name="bf" type="v8bf16"/>
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<field name="f" type="v8f"/>
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<field name="u" type="v8u"/>
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<field name="s" type="v8i"/>
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</union>
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<union id="vnb">
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<field name="u" type="v16u"/>
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<field name="s" type="v16i"/>
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</union>
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<union id="vnq">
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<field name="u" type="v1u"/>
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<field name="s" type="v1i"/>
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</union>
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<union id="aarch64v">
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<field name="d" type="vnd"/>
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<field name="s" type="vns"/>
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<field name="h" type="vnh"/>
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<field name="b" type="vnb"/>
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<field name="q" type="vnq"/>
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</union>
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<reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
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<reg name="v1" bitsize="128" type="aarch64v" />
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<reg name="v2" bitsize="128" type="aarch64v" />
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<reg name="v3" bitsize="128" type="aarch64v" />
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<reg name="v4" bitsize="128" type="aarch64v" />
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<reg name="v5" bitsize="128" type="aarch64v" />
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<reg name="v6" bitsize="128" type="aarch64v" />
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<reg name="v7" bitsize="128" type="aarch64v" />
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<reg name="v8" bitsize="128" type="aarch64v" />
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<reg name="v9" bitsize="128" type="aarch64v" />
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<reg name="v10" bitsize="128" type="aarch64v"/>
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<reg name="v11" bitsize="128" type="aarch64v"/>
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<reg name="v12" bitsize="128" type="aarch64v"/>
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<reg name="v13" bitsize="128" type="aarch64v"/>
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<reg name="v14" bitsize="128" type="aarch64v"/>
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<reg name="v15" bitsize="128" type="aarch64v"/>
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<reg name="v16" bitsize="128" type="aarch64v"/>
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<reg name="v17" bitsize="128" type="aarch64v"/>
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<reg name="v18" bitsize="128" type="aarch64v"/>
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<reg name="v19" bitsize="128" type="aarch64v"/>
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<reg name="v20" bitsize="128" type="aarch64v"/>
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<reg name="v21" bitsize="128" type="aarch64v"/>
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<reg name="v22" bitsize="128" type="aarch64v"/>
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<reg name="v23" bitsize="128" type="aarch64v"/>
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<reg name="v24" bitsize="128" type="aarch64v"/>
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<reg name="v25" bitsize="128" type="aarch64v"/>
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<reg name="v26" bitsize="128" type="aarch64v"/>
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<reg name="v27" bitsize="128" type="aarch64v"/>
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<reg name="v28" bitsize="128" type="aarch64v"/>
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<reg name="v29" bitsize="128" type="aarch64v"/>
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<reg name="v30" bitsize="128" type="aarch64v"/>
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<reg name="v31" bitsize="128" type="aarch64v"/>
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<flags id="fpsr_flags" size="4">
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<!-- Invalid Operation cumulative floating-point exception bit. -->
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<field name="IOC" start="0" end="0"/>
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<!-- Divide by Zero cumulative floating-point exception bit. -->
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<field name="DZC" start="1" end="1"/>
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<!-- Overflow cumulative floating-point exception bit. -->
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<field name="OFC" start="2" end="2"/>
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<!-- Underflow cumulative floating-point exception bit. -->
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<field name="UFC" start="3" end="3"/>
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<!-- Inexact cumulative floating-point exception bit.. -->
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<field name="IXC" start="4" end="4"/>
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<!-- Input Denormal cumulative floating-point exception bit. -->
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<field name="IDC" start="7" end="7"/>
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<!-- Cumulative saturation bit, Advanced SIMD only. -->
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<field name="QC" start="27" end="27"/>
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<!-- When AArch32 is supported at any Exception level and AArch32
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floating-point is implemented: Overflow condition flag for AArch32
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floating-point comparison operations. -->
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<field name="V" start="28" end="28"/>
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<!-- When AArch32 is supported at any Exception level and AArch32
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floating-point is implemented:
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Carry condition flag for AArch32 floating-point comparison operations.
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-->
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<field name="C" start="29" end="29"/>
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<!-- When AArch32 is supported at any Exception level and AArch32
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floating-point is implemented:
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Zero condition flag for AArch32 floating-point comparison operations.
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-->
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<field name="Z" start="30" end="30"/>
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<!-- When AArch32 is supported at any Exception level and AArch32
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floating-point is implemented:
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Negative condition flag for AArch32 floating-point comparison
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operations. -->
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<field name="N" start="31" end="31"/>
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</flags>
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<reg name="fpsr" bitsize="32" type="fpsr_flags"/>
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<flags id="fpcr_flags" size="4">
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<!-- Flush Inputs to Zero (part of Armv8.7). -->
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<field name="FIZ" start="0" end="0"/>
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<!-- Alternate Handling (part of Armv8.7). -->
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<field name="AH" start="1" end="1"/>
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<!-- Controls how the output elements other than the lowest element of the
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vector are determined for Advanced SIMD scalar instructions (part of
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Armv8.7). -->
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<field name="NEP" start="2" end="2"/>
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<!-- Invalid Operation floating-point exception trap enable. -->
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<field name="IOE" start="8" end="8"/>
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<!-- Divide by Zero floating-point exception trap enable. -->
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<field name="DZE" start="9" end="9"/>
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<!-- Overflow floating-point exception trap enable. -->
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<field name="OFE" start="10" end="10"/>
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<!-- Underflow floating-point exception trap enable. -->
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<field name="UFE" start="11" end="11"/>
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<!-- Inexact floating-point exception trap enable. -->
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<field name="IXE" start="12" end="12"/>
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<!-- The value of this bit controls the numeric behaviors of BFloat16 dot
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product calculations performed by the BFDOT, BFMMLA, BFMOPA, and
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BFMOPS instructions when FEAT_EBF16 is implemented. -->
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<field name="EBF" start="13" end="13"/>
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<!-- Input Denormal floating-point exception trap enable. -->
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<field name="IDE" start="15" end="15"/>
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<!-- This field has no function in AArch64 state, and non-zero values are
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ignored during execution in AArch64 state.
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This field is included only for context saving and restoration of
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the AArch32 FPSCR.Len field. -->
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<field name="Len" start="16" end="18"/>
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<!-- Flush-to-zero mode control bit on half-precision data-processing
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instructions. -->
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<field name="FZ16" start="19" end="19"/>
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<!-- This field has no function in AArch64 state, and non-zero values are
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ignored during execution in AArch64 state.
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This field is included only for context saving and restoration of the
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AArch32 FPSCR.Stride field. -->
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<field name="Stride" start="20" end="21"/>
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<!-- Rounding Mode control field. -->
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<field name="RMode" start="22" end="23"/>
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<!-- Flush-to-zero mode control bit. -->
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<field name="FZ" start="24" end="24"/>
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<!-- Default NaN mode control bit. -->
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<field name="DN" start="25" end="25"/>
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<!-- Alternative half-precision control bit. -->
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<field name="AHP" start="26" end="26"/>
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</flags>
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<reg name="fpcr" bitsize="32" type="fpcr_flags"/>
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</feature>
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