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78a3b0fab8
Collects information during the prologue scan and uses this to unwind registers when no DWARF information is available. This patch has been tested by disabling the DWARF stack unwinders, and running the complete GDB testsuite against a range of RISC-V targets. The results are comparable to running with the DWARF unwinders in place. gdb/ChangeLog: * riscv-tdep.c: Add 'prologue-value.h' include. (struct riscv_unwind_cache): New struct. (riscv_debug_unwinder): New global. (riscv_scan_prologue): Update arguments, capture register details from prologue scan. (riscv_skip_prologue): Reformat arguments line, move end of prologue calculation into riscv_scan_prologue. (riscv_frame_cache): Update return type, create riscv_unwind_cache, scan the prologue, and fill in remaining cache details. (riscv_frame_this_id): Use frame id computed in riscv_frame_cache. (riscv_frame_prev_register): Use the trad_frame within the riscv_unwind_cache. (_initialize_riscv_tdep): Add 'set/show debug riscv unwinder' flag.
91 lines
2.9 KiB
C++
91 lines
2.9 KiB
C++
/* Target-dependent header for the RISC-V architecture, for GDB, the
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GNU Debugger.
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Copyright (C) 2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef RISCV_TDEP_H
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#define RISCV_TDEP_H
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/* RiscV register numbers. */
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enum
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{
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RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
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RISCV_RA_REGNUM = 1, /* Return Address. */
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RISCV_SP_REGNUM = 2, /* Stack Pointer. */
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RISCV_GP_REGNUM = 3, /* Global Pointer. */
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RISCV_TP_REGNUM = 4, /* Thread Pointer. */
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RISCV_FP_REGNUM = 8, /* Frame Pointer. */
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RISCV_A0_REGNUM = 10, /* First argument. */
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RISCV_A1_REGNUM = 11, /* Second argument. */
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RISCV_PC_REGNUM = 32, /* Program Counter. */
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RISCV_NUM_INTEGER_REGS = 32,
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RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
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RISCV_FA0_REGNUM = 43,
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RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
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RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
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RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
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#define DECLARE_CSR(name, num) \
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RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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RISCV_LAST_CSR_REGNUM = 4160,
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RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
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RISCV_PRIV_REGNUM = 4161,
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RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
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};
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/* RISC-V specific per-architecture information. */
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struct gdbarch_tdep
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{
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union
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{
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/* Provide access to the whole ABI in one value. */
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unsigned value;
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struct
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{
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/* Encode the base machine length following the same rules as in the
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MISA register. */
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unsigned base_len : 2;
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/* Encode which floating point ABI is in use following the same rules
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as the ELF e_flags field. */
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unsigned float_abi : 2;
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} fields;
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} abi;
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/* Only the least significant 26 bits are (possibly) valid, and indicate
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features that are supported on the target. These could be cached from
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the target, or read from the executable when available. */
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unsigned core_features;
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};
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/* Return the width in bytes of the general purpose registers for GDBARCH. */
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extern int riscv_isa_xlen (struct gdbarch *gdbarch);
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/* Single step based on where the current instruction will take us. */
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extern std::vector<CORE_ADDR> riscv_software_single_step
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(struct regcache *regcache);
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#endif /* RISCV_TDEP_H */
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