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106 lines
3.8 KiB
C
106 lines
3.8 KiB
C
/* Simulator header for cgen cpus.
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Copyright (C) 1998-2017 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CGEN_CPU_H
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#define CGEN_CPU_H
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/* Type of function that is ultimately called by sim_resume. */
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typedef void (ENGINE_FN) (SIM_CPU *);
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/* Type of function to do disassembly. */
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typedef void (CGEN_DISASSEMBLER) (SIM_CPU *, const CGEN_INSN *,
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const ARGBUF *, IADDR pc_, char *buf_);
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/* Additional non-machine generated per-cpu data to go in SIM_CPU.
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The member's name must be `cgen_cpu'. */
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typedef struct {
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/* Non-zero while cpu simulation is running. */
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int running_p;
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#define CPU_RUNNING_P(cpu) ((cpu)->cgen_cpu.running_p)
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/* Instruction count. This is maintained even in fast mode to keep track
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of simulator speed. */
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unsigned long insn_count;
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#define CPU_INSN_COUNT(cpu) ((cpu)->cgen_cpu.insn_count)
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/* sim_resume handlers */
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ENGINE_FN *fast_engine_fn;
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#define CPU_FAST_ENGINE_FN(cpu) ((cpu)->cgen_cpu.fast_engine_fn)
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ENGINE_FN *full_engine_fn;
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#define CPU_FULL_ENGINE_FN(cpu) ((cpu)->cgen_cpu.full_engine_fn)
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/* Maximum number of instructions per time slice.
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When single stepping this is 1. If using the pbb model, this can be
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more than 1. 0 means "as long as you want". */
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unsigned int max_slice_insns;
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#define CPU_MAX_SLICE_INSNS(cpu) ((cpu)->cgen_cpu.max_slice_insns)
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/* Simulator's execution cache.
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Allocate space for this even if not used as some simulators may have
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one machine variant that uses the scache and another that doesn't and
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we don't want members in this struct to move about. */
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CPU_SCACHE scache;
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/* Instruction descriptor table. */
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IDESC *idesc;
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#define CPU_IDESC(cpu) ((cpu)->cgen_cpu.idesc)
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/* Whether the read,write,semantic entries (function pointers or computed
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goto labels) have been initialized or not. */
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int idesc_read_init_p;
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#define CPU_IDESC_READ_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_read_init_p)
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int idesc_write_init_p;
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#define CPU_IDESC_WRITE_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_write_init_p)
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int idesc_sem_init_p;
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#define CPU_IDESC_SEM_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_sem_init_p)
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/* Cpu descriptor table.
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This is a CGEN created entity that contains the description file
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turned into C code and tables for our use. */
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CGEN_CPU_DESC cpu_desc;
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#define CPU_CPU_DESC(cpu) ((cpu)->cgen_cpu.cpu_desc)
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/* Function to fetch the insn data entry in the IDESC. */
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const CGEN_INSN * (*get_idata) (SIM_CPU *, int);
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#define CPU_GET_IDATA(cpu) ((cpu)->cgen_cpu.get_idata)
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/* Floating point support. */
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CGEN_FPU fpu;
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#define CGEN_CPU_FPU(cpu) (& (cpu)->cgen_cpu.fpu)
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/* Disassembler. */
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CGEN_DISASSEMBLER *disassembler;
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#define CPU_DISASSEMBLER(cpu) ((cpu)->cgen_cpu.disassembler)
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/* Queued writes for parallel write-after support. */
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CGEN_WRITE_QUEUE write_queue;
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#define CPU_WRITE_QUEUE(cpu) (& (cpu)->cgen_cpu.write_queue)
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/* Allow slop in size calcs for case where multiple cpu types are supported
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and space for the specified cpu is malloc'd at run time. */
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double slop;
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} CGEN_CPU;
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/* Shorthand macro for fetching registers.
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CPU_CGEN_HW is defined in cpu.h. */
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#define CPU(x) (CPU_CGEN_HW (current_cpu)->x)
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#endif /* CGEN_CPU_H */
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