binutils-gdb/sim/riscv
Mike Frysinger d5a71b1131 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code
Every arch handles this the same way, so move it to the common code.
This will also make unifying the sim_cpu structure easier.
2021-04-12 00:14:32 -04:00
..
aclocal.m4 sim: unify toolchain settings 2021-04-02 23:31:14 -04:00
ChangeLog sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
config.in
configure sim: unify toolchain settings 2021-04-02 23:31:14 -04:00
configure.ac sim: common: split up acinclude.m4 into individual m4 files 2021-02-21 02:20:19 -05:00
interp.c sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
machs.c
machs.h
Makefile.in
model_list.def
sim-main.c RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 2021-02-19 11:44:49 +08:00
sim-main.h