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6b230f1b26
handling. * config/arm/tm-arm.h (COERCE_FLOAT_TO_DOUBLE): Define to call standard_coerce_float_to_double().
79 lines
3.2 KiB
C
79 lines
3.2 KiB
C
/* Definitions to target GDB to ARM targets.
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Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997,
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1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#ifndef TM_ARM_H
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#define TM_ARM_H
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#ifndef GDB_MULTI_ARCH
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#define GDB_MULTI_ARCH 1
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#endif
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/* The following define instruction sequences that will cause ARM
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cpu's to take an undefined instruction trap. These are used to
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signal a breakpoint to GDB.
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The newer ARMv4T cpu's are capable of operating in ARM or Thumb
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modes. A different instruction is required for each mode. The ARM
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cpu's can also be big or little endian. Thus four different
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instructions are needed to support all cases.
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Note: ARMv4 defines several new instructions that will take the
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undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
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not in fact add the new instructions. The new undefined
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instructions in ARMv4 are all instructions that had no defined
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behaviour in earlier chips. There is no guarantee that they will
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raise an exception, but may be treated as NOP's. In practice, it
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may only safe to rely on instructions matching:
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3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
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Even this may only true if the condition predicate is true. The
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following use a condition predicate of ALWAYS so it is always TRUE.
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There are other ways of forcing a breakpoint. ARM Linux, RISC iX,
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and NetBSD will all use a software interrupt rather than an
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undefined instruction to force a trap. This can be handled by
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redefining some or all of the following in a target dependent
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fashion. */
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#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
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#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
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#define THUMB_LE_BREAKPOINT {0xfe,0xdf}
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#define THUMB_BE_BREAKPOINT {0xdf,0xfe}
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/* Specify that for the native compiler variables for a particular
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lexical context are listed after the beginning LBRAC instead of
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before in the executables list of symbols. */
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#define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
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/* XXX This is NOT multi-arch compatible. */
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#define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
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extern int arm_call_dummy_breakpoint_offset (void);
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/* The first 0x20 bytes are the trap vectors. */
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#define LOWEST_PC 0x20
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#define COERCE_FLOAT_TO_DOUBLE(formal, actual) (standard_coerce_float_to_double (formal, actual))
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#endif /* TM_ARM_H */
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