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https://sourceware.org/git/binutils-gdb.git
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d8ba1c4037
CCMP and CTEST are two new sets of instructions for conditional CMP
and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST
in the instruction mnemonic, e.g.:
ccmp<cc> { dfv=sf , cf , of } %eax, %ecx
also add
{evex} cmp/test %eax, %ecx
as an alias for ccmpt.
For the encoder part, add function check_Scc_OszcOperation to parse
'{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode,
and adjust base_opcode to its normal meaning in install_template.
For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags
suffixes.
gas/ChangeLog:
* config/tc-i386.c (OSZC_CF): New.
(OSZC_ZF): Ditto.
(OSZC_SF): Ditto.
(OSZC_OF): Ditto.
(set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice.
(check_Scc_OszcOperations): Handle SCC OSZC flags.
(install_template): Add scc and oszc_flags.
(build_apx_evex_prefix): Encode SCC and oszc flags bits.
(parse_insn): Handle check_Scc_OszcOperations.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-reg.h: Add ccmp and ctest.
* i386-dis-evex.h: Ditto.
* i386-dis.c (struct instr_info): add scc.
(struct dis386): Add new micro 'NE','SC' and'DF'.
(get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn.
(putop): Handle %NE, %SC and %DF.
* i386-opc.h (SCC): New.
* i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Ditto.
126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/* REG_EVEX_0F71 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "%XEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ "%XEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ "%XEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* REG_EVEX_0F72 */
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{
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{ "vpror%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ VEX_W_TABLE (EVEX_W_0F72_R_2) },
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{ Bad_Opcode },
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{ "%XEvpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F72_R_6) },
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},
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/* REG_EVEX_0F73 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F73_R_2) },
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{ "%XEvpsrldqY", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F73_R_6) },
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{ "%XEvpslldqY", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* REG_EVEX_0F38C6_L_2 */
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{
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{ Bad_Opcode },
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{ "vgatherpf0dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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{ "vgatherpf1dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vscatterpf0dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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{ "vscatterpf1dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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},
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/* REG_EVEX_0F38C7_L_2 */
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{
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{ Bad_Opcode },
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{ "vgatherpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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{ "vgatherpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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{ "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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},
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/* REG_EVEX_MAP4_80 */
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{
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{ "%NFaddA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "%NForA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "adcA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "sbbA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "%NFandA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "%NFsubA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "%NFxorA", { VexGb, Eb, Ib }, NO_PREFIX },
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{ "%NEccmp%SCA%DF", { Eb, Ib }, NO_PREFIX },
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},
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/* REG_EVEX_MAP4_81 */
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{
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{ "%NFaddQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "%NForQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "adcQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "sbbQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "%NFandQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "%NFsubQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "%NFxorQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "%NEccmp%SCQ%DF", { Ev, Iv }, PREFIX_NP_OR_DATA },
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},
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/* REG_EVEX_MAP4_83 */
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{
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{ "%NFaddQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "%NForQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "adcQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "sbbQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "%NFandQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "%NFsubQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "%NFxorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
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{ "%NEccmp%SCQ%DF", { Ev, sIb }, PREFIX_NP_OR_DATA },
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},
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/* REG_EVEX_MAP4_8F */
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{
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{ VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) },
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},
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/* REG_EVEX_MAP4_F6 */
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{
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{ "%NEctest%SCA%DF", { Eb, Ib }, NO_PREFIX },
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{ "%NEctest%SCA%DF", { Eb, Ib }, NO_PREFIX },
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{ "notA", { VexGb, Eb }, NO_PREFIX },
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{ "%NFnegA", { VexGb, Eb }, NO_PREFIX },
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{ "%NFmulA", { Eb }, NO_PREFIX },
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{ "%NFimulA", { Eb }, NO_PREFIX },
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{ "%NFdivA", { Eb }, NO_PREFIX },
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{ "%NFidivA", { Eb }, NO_PREFIX },
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},
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/* REG_EVEX_MAP4_F7 */
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{
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{ "%NEctest%SCQ%DF", { Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "%NEctest%SCQ%DF", { Ev, Iv }, PREFIX_NP_OR_DATA },
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{ "notQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
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{ "%NFnegQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
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{ "%NFmulQ", { Ev }, PREFIX_NP_OR_DATA },
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{ "%NFimulQ", { Ev }, PREFIX_NP_OR_DATA },
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{ "%NFdivQ", { Ev }, PREFIX_NP_OR_DATA },
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{ "%NFidivQ", { Ev }, PREFIX_NP_OR_DATA },
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},
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/* REG_EVEX_MAP4_FE */
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{
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{ "%NFincA", { VexGb, Eb }, NO_PREFIX },
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{ "%NFdecA", { VexGb, Eb }, NO_PREFIX },
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},
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/* REG_EVEX_MAP4_FF */
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{
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{ "%NFincQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
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{ "%NFdecQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) },
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},
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