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69abc51c17
* ppc-linux-nat.c (ppc_register_u_addr): Add special case to return offset for full 64-bit slot of FPSCR when in 32-bits. (ppc_linux_read_description): Return target description with 64-bit FPSCR when inferior is running on an ISA 2.05 or later processor. * ppc-linux-tdep.c (_initialize_ppc_linux_tdep): Call initialize_tdec_powerpc_isa205_32l, initialize_tdec_powerpc_isa205_altivec32l, initialize_tdec_powerpc_isa205_vsx32l, initialize_tdec_powerpc_isa205_64l, initialize_tdec_powerpc_isa205_altivec64l and initialize_tdec_powerpc_isa205_vsx64l. * ppc-linux-tdep.h: Add external declaration for tdesc_powerpc_isa205_32l, tdesc_powerpc_isa205_altivec32l, tdesc_powerpc_isa205_vsx32l, tdesc_powerpc_isa205_64l, tdesc_powerpc_isa205_altivec64l and tdesc_powerpc_isa205_vsx64l. * features/rs600/powerpc-fpu-isa205.xml: New file. * features/rs600/powerpc-isa205-32l.xml: New file. * features/rs600/powerpc-isa205-64l.xml: New file. * features/rs600/powerpc-isa205-altivec32l.xml: New file. * features/rs600/powerpc-isa205-altivec64l.xml: New file. * features/rs600/powerpc-isa205-vsx32l.xml: New file. * features/rs600/powerpc-isa205-vsx64l.xml: New file. * features/rs600/powerpc-isa205-32l.c: Generate. * features/rs600/powerpc-isa205-64l.c: Generate. * features/rs600/powerpc-isa205-altivec32l.c: Generate. * features/rs600/powerpc-isa205-altivec64l.c: Generate. * features/rs600/powerpc-isa205-vsx32l.c: Generate. * features/rs600/powerpc-isa205-vsx64l.c: Generate. gdb/testsuite/ * gdb.arch/ppc-dfp.exp: New file. * gdb.arch/ppc-dfp.c: New file.
45 lines
2.1 KiB
XML
45 lines
2.1 KiB
XML
<?xml version="1.0"?>
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<!-- Copyright (C) 2007, 2008 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.power.fpu">
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<reg name="f0" bitsize="64" type="ieee_double" regnum="32"/>
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<reg name="f1" bitsize="64" type="ieee_double"/>
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<reg name="f2" bitsize="64" type="ieee_double"/>
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<reg name="f3" bitsize="64" type="ieee_double"/>
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<reg name="f4" bitsize="64" type="ieee_double"/>
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<reg name="f5" bitsize="64" type="ieee_double"/>
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<reg name="f6" bitsize="64" type="ieee_double"/>
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<reg name="f7" bitsize="64" type="ieee_double"/>
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<reg name="f8" bitsize="64" type="ieee_double"/>
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<reg name="f9" bitsize="64" type="ieee_double"/>
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<reg name="f10" bitsize="64" type="ieee_double"/>
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<reg name="f11" bitsize="64" type="ieee_double"/>
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<reg name="f12" bitsize="64" type="ieee_double"/>
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<reg name="f13" bitsize="64" type="ieee_double"/>
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<reg name="f14" bitsize="64" type="ieee_double"/>
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<reg name="f15" bitsize="64" type="ieee_double"/>
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<reg name="f16" bitsize="64" type="ieee_double"/>
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<reg name="f17" bitsize="64" type="ieee_double"/>
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<reg name="f18" bitsize="64" type="ieee_double"/>
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<reg name="f19" bitsize="64" type="ieee_double"/>
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<reg name="f20" bitsize="64" type="ieee_double"/>
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<reg name="f21" bitsize="64" type="ieee_double"/>
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<reg name="f22" bitsize="64" type="ieee_double"/>
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<reg name="f23" bitsize="64" type="ieee_double"/>
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<reg name="f24" bitsize="64" type="ieee_double"/>
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<reg name="f25" bitsize="64" type="ieee_double"/>
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<reg name="f26" bitsize="64" type="ieee_double"/>
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<reg name="f27" bitsize="64" type="ieee_double"/>
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<reg name="f28" bitsize="64" type="ieee_double"/>
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<reg name="f29" bitsize="64" type="ieee_double"/>
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<reg name="f30" bitsize="64" type="ieee_double"/>
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<reg name="f31" bitsize="64" type="ieee_double"/>
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<reg name="fpscr" bitsize="64" group="float" regnum="70"/>
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</feature>
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