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3224e32fb8
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.
Approved-By: Andrew Burgess <aburgess@redhat.com>
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| .. | ||
| aarch64 | ||
| arm | ||
| avr | ||
| bfin | ||
| bpf | ||
| common | ||
| config | ||
| cr16 | ||
| cris | ||
| d10v | ||
| example-synacor | ||
| frv | ||
| ft32 | ||
| h8300 | ||
| iq2000 | ||
| lib | ||
| lm32 | ||
| m32c | ||
| m32r | ||
| m68hc11 | ||
| mcore | ||
| microblaze | ||
| mips | ||
| mn10300 | ||
| moxie | ||
| msp430 | ||
| or1k | ||
| pru | ||
| riscv | ||
| sh | ||
| v850 | ||
| .gitignore | ||
| ChangeLog-2021 | ||
| local.mk | ||