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The SME (Scalable Matrix Extension) [1] exposes a new matrix register ZA with variable sizes. It also exposes a new mode called streaming mode. Similarly to SVE, the ZA register size is dictated by a vector length, but the SME vector length is called streaming vetor length. The total size for ZA in a given moment is svl x svl. In streaming mode, the SVE registers have their sizes based on svl rather than the regular vector length (vl). The feature detection is controlled by the HWCAP2_SME bit, but actual support should be validated by attempting a ptrace call for one of the new register sets: NT_ARM_ZA and NT_ARM_SSVE. Due to its large size, the ZA register is exposed as a vector of bytes, but we introduce a number of pseudo-registers that gives various different views into the ZA contents. These can be arranged in a couple categories: tiles and tile slices. Tiles are matrices the same size or smaller than ZA. Tile slices are vectors which map to ZA's rows/columns in different ways. A new dynamic target description is provided containing the ZA register, the SVG register and the SVCR register. The size of ZA, like the SVE vector registers, is based on the vector length register SVG (VG for SVE). This patch enables SME register support for gdb. [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture Co-Authored-By: Ezra Sitorus <ezra.sitorus@arm.com> Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
155 lines
5.7 KiB
C
155 lines
5.7 KiB
C
/* Common native Linux definitions for the AArch64 scalable
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extensions: SVE and SME.
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Copyright (C) 2018-2023 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef NAT_AARCH64_SCALABLE_LINUX_PTRACE_H
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#define NAT_AARCH64_SCALABLE_LINUX_PTRACE_H
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#include <signal.h>
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#include <sys/utsname.h>
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/* The order in which <sys/ptrace.h> and <asm/ptrace.h> are included
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can be important. <sys/ptrace.h> often declares various PTRACE_*
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enums. <asm/ptrace.h> often defines preprocessor constants for
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these very same symbols. When that's the case, build errors will
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result when <asm/ptrace.h> is included before <sys/ptrace.h>. */
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#include <sys/ptrace.h>
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#include <asm/ptrace.h>
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#include <stdarg.h>
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#include "aarch64-scalable-linux-ptrace.h"
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#include "aarch64-scalable-linux-sigcontext.h"
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/* Indicates whether a SVE ptrace header is followed by SVE registers or a
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fpsimd structure. */
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#define HAS_SVE_STATE(header) ((header).flags & SVE_PT_REGS_SVE)
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/* Return true if there is an active SVE state in TID.
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Return false otherwise. */
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bool aarch64_has_sve_state (int tid);
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/* Return true if there is an active SSVE state in TID.
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Return false otherwise. */
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bool aarch64_has_ssve_state (int tid);
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/* Return true if there is an active ZA state in TID.
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Return false otherwise. */
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bool aarch64_has_za_state (int tid);
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/* Given TID, read the SVE header into HEADER.
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Return true if successful, false otherwise. */
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bool read_sve_header (int tid, struct user_sve_header &header);
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/* Given TID, store the SVE HEADER.
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Return true if successful, false otherwise. */
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bool write_sve_header (int tid, const struct user_sve_header &header);
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/* Given TID, read the SSVE header into HEADER.
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Return true if successful, false otherwise. */
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bool read_ssve_header (int tid, struct user_sve_header &header);
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/* Given TID, store the SSVE HEADER.
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Return true if successful, false otherwise. */
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bool write_ssve_header (int tid, const struct user_sve_header &header);
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/* Given TID, read the ZA header into HEADER.
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Return true if successful, false otherwise. */
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bool read_za_header (int tid, struct user_za_header &header);
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/* Given TID, store the ZA HEADER.
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Return true if successful, false otherwise. */
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bool write_za_header (int tid, const struct user_za_header &header);
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/* Read VQ for the given tid using ptrace. If SVE is not supported then zero
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is returned (on a system that supports SVE, then VQ cannot be zero). */
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uint64_t aarch64_sve_get_vq (int tid);
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/* Set VQ in the kernel for the given tid, using either the value VQ or
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reading from the register VG in the register buffer. */
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bool aarch64_sve_set_vq (int tid, uint64_t vq);
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bool aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf);
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/* Read the streaming mode vq (svq) for the given TID. If the ZA state is not
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supported or active, return 0. */
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uint64_t aarch64_za_get_svq (int tid);
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/* Set the vector quotient (vq) in the kernel for the given TID using the
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value VQ.
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Return true if successful, false otherwise. */
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bool aarch64_za_set_svq (int tid, uint64_t vq);
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bool aarch64_za_set_svq (int tid, const struct reg_buffer_common *reg_buf,
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int svg_regnum);
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/* Given TID, return the SVE/SSVE data as a vector of bytes. */
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extern gdb::byte_vector aarch64_fetch_sve_regset (int tid);
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/* Write the SVE/SSVE contents from SVE_STATE to TID. */
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extern void aarch64_store_sve_regset (int tid,
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const gdb::byte_vector &sve_state);
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/* Given TID, return the ZA data as a vector of bytes. */
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extern gdb::byte_vector aarch64_fetch_za_regset (int tid);
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/* Write ZA_STATE for TID. */
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extern void aarch64_store_za_regset (int tid, const gdb::byte_vector &za_state);
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/* Given TID, initialize the ZA register set so the header contains the right
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size. The bytes of the ZA register are initialized to zero. */
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extern void aarch64_initialize_za_regset (int tid);
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/* Given a register buffer REG_BUF, update it with SVE/SSVE register data
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from SVE_STATE. */
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extern void
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aarch64_sve_regs_copy_to_reg_buf (int tid, struct reg_buffer_common *reg_buf);
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/* Given a thread id TID and a register buffer REG_BUF containing SVE/SSVE
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register data, write the SVE data to thread TID. */
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extern void
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aarch64_sve_regs_copy_from_reg_buf (int tid,
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struct reg_buffer_common *reg_buf);
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/* Given a thread id TID and a register buffer REG_BUF, update the register
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buffer with the ZA state from thread TID.
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ZA_REGNUM, SVG_REGNUM and SVCR_REGNUM are the register numbers for ZA,
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SVG and SVCR registers. */
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extern void aarch64_za_regs_copy_to_reg_buf (int tid,
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struct reg_buffer_common *reg_buf,
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int za_regnum, int svg_regnum,
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int svcr_regnum);
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/* Given a thread id TID and a register buffer REG_BUF containing ZA register
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data, write the ZA data to thread TID.
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ZA_REGNUM, SVG_REGNUM and SVCR_REGNUM are the register numbers for ZA,
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SVG and SVCR registers. */
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extern void
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aarch64_za_regs_copy_from_reg_buf (int tid,
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struct reg_buffer_common *reg_buf,
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int za_regnum, int svg_regnum,
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int svcr_regnum);
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#endif /* NAT_AARCH64_SCALABLE_LINUX_PTRACE_H */
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